|Design||manycore extended x86/x64 design|
|General purpose||Intel Architecture registers|
|Floating point||512-bit SIMD vector registers|
Intel Many Integrated Core Architecture or Intel MIC (pronounced Mike) is a multiprocessor computer architecture developed by Intel incorporating earlier work on the Larrabee many core architecture, the Teraflops Research Chip multicore chip research project, and the Intel Single-chip Cloud Computer multicore microprocessor.
Prototype products codenamed Knights Ferry were announced and released to developers in 2010. A commercial release, codenamed Knights Corner to be built on a 22nm process is scheduled to go into production in late 2012.
In September 2011, the Texas Advanced Computing Center (TACC) announced it would use Knights Corner cards in their 10 PetaFLOPS "Stampede" supercomputer, providing 8 PetaFLOPS of computing power.
At the International Supercomputing Conference (2012, Hamburg), Intel announced the branding of the processor product family as Intel Xeon Phi.
The Larrabee microarchitecture (in development since 2006) introduced very wide (512-bit) SIMD units to a x86 architecture based processor design, extended to a cache coherent multiprocessor system connected via a ring bus to memory; each core was capable of 4-way multi-threading. Due to the design being intended for GPU as well as general purpose computing the Larrabee chips also included specialised hardware for texture sampling. The project to produce a GPU retail product directly from the Larrabee research project was terminated in May 2010.
Another contemporary Intel research project implementing x86 architecture on a many-multicore processor was the 'Single Chip Cloud Computer', (prototype introduced 2009.), a design mimicking a cloud computing computer datacentre on a single chip with multiple independent cores - the prototype design included 48 cores per chip with hardware support for selective frequency and voltage control of cores to maximize energy efficiency, and incorporated a mesh network for interchip messaging. The design lacked cache coherent cores and focussed on principles that would allow the design to scale to many more cores.
The Teraflops Research Chip (prototype unveiled 2007) was an experimental 80 core chip with two floating point units per core implementing a 96-bit VLIW architecture. The project investigated intercore communication methods, per-chip power management, and achieved 1.01 TFLOPS at 3.16 GHz consuming 62 W of power.
Knights Ferry 
Intel's MIC prototype board, named Knights Ferry, incorporating a processor codenamed Aubrey Isle was announced 31 May 2010. The product was stated to be a derivative of the Larrabee project and other Intel research including the Single-chip Cloud Computer.
The development product was offered as a PCIe card with 32 in-order cores at up to 1.2 GHz with 4 threads per core, 2 GB GDDR5 memory, and 8 MB coherent L2 cache (256 kB per core with 32 kB L1 cache), and a power requirement of ~300 W, built at a 45 nm process. In the Aubrey Isle core a 1,024-bit ring bus (512-bit bi-directional) connects processors to main memory. Single board performance has exceeded 750 GFLOPS. The prototype boards only support single precision floating point instructions.
Initial developers included CERN, Korea Institute of Science and Technology Information (KISTI) and Leibniz Supercomputing Centre. Hardware vendors for prototype boards included IBM, SGI, HP, Dell and others.
Knights Corner 
The Knights Corner product line is expected to be made at a 22 nm process size, using Intel's Tri-gate technology with more than 50 cores per chip, and is expected to lead to commercial products.
In June 2011, SGI announced a partnership with Intel to utilize the MIC architecture in its high performance computing products. In September 2011, it was announced that the Texas Advanced Computing Center (TACC) will use Knights Corner cards in their 10 PetaFLOPS "Stampede" supercomputer, providing 8 PetaFLOPS of the compute power. According to "Stampede: A Comprehensive Petascale Computing Environment" the "second generation Intel (Knights Landing) MICs will be added when they become available, increasing Stampede's aggregate peak performance to at least 15 PetaFLOPS."
On June 5, 2012, Intel released open source software and documentation regarding Knights Corner.
In June 2012, ScaleMP announced it will provide its virtualization software to allows using 'Knight's Corner' chips (branded as 'Xeon Phi') as main processor transparent extension. The virtualization software will allow 'Knight's Corner' to run legacy MMX/SSE code and access unlimited amount of (host) memory without need for code changes.
Knights Landing 
Code name for the second generation MIC architecture processor line from Intel.
Xeon Phi 
On November 12, 2012, Intel announced two Xeon Phi coprocessor families which are the Xeon Phi 3100 and the Xeon Phi 5110P. The Xeon Phi 3100 will be capable of more than 1 teraflops of double precision floating point instructions with 240GB/sec memory bandwidth at 300 W. The Xeon Phi 5110P will be capable of 1.01 teraflops of double precision floating point instructions with 320GB/sec memory bandwidth at 225 W. The Xeon Phi uses the 22 nm process size. The Xeon Phi 3100 will be priced at under US$2,000 while the Xeon Phi 5110P will have a price of US$2,649.
The cores of Intel MIC are based on a modified version of P54C design, used in the original Pentium. The basis of the Intel MIC architecture is to leverage x86 legacy by creating a x86-compatible multiprocessor architecture that can utilize existing parallelization software tools. Programming tools include OpenMP, OpenCL, Intel Cilk Plus and specialised versions of Intel's Fortran, C++ and math libraries.
Design elements inherited from the Larrabee project include x86 ISA, 512-bit SIMD units, coherent L2 cache, and ultra-wide ring bus connecting processors and memory.
See also 
- Charlie Demerjian (3 July 2006), "New from Intel: It's Mini-Cores!", www.theinquirer.net (The Inquirer)
- Seiler, L.; Carmean, D.; Sprangle, E.; Forsyth, T.; Abrash, M.; Dubey, P.; Junkins, S.; Lake, A.; Sugerman, J.; Cavin, R.; Espasa, R.; Grochowski, E.; Juan, T.; Hanrahan, P. (August 2008). "Larrabee: A Many-Core x86 Architecture for Visual Computing" (PDF). ACM Transactions on Graphics. Proceedings of ACM SIGGRAPH 2008 27 (3): 18:11–18:11. doi:10.1145/1360612.1360617. ISSN 0730-0301. Retrieved 2008-08-06.
- Tom Forsyth, "SIMD Programming with Larrabee", www.stanford.edu (Intel)
- Ryan Smith (25 May 2010), "Intel Kills Larrabee GPU, Will Not Bring a Discrete Graphics Product to Market\", www.anandtech.com (AnandTech)
- Tony Bradley (3 December 2009), "Intel 48-Core "Single-Chip Cloud Computer" Improves Power Efficiency", www.pcworld.com (PCWorld)
- "Intel Research : Single-Chip Cloud Computer", techresearch.intel.com (Intel)
- Ben Ames (11 February 2007), "Intel Tests Chip Design With 80-Core Processor", www.pcworld.com (IDG News)
- "Intel’s Teraflops Research Chip", download.intel.com (Intel)
- Anton Shilov (12 February 2007), "Intel Details 80-Core Teraflops Research Chip", www.xbitlabs.com (Xbit laboratories)
- Rupert Goodwins (1 June 2010), "Intel unveils many-core Knights platform for HPC", www.zdnet.co.uk (ZDNet)
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- Mike Giles (24 June 2010), "Runners and riders in GPU steeplechase", people.maths.ox.ac.uk: 8–10
- "Fast Sort on CPUs, GPUs and Intel MIC Architectures", techresearch.intel.com (Intel), "Section 2.2 Radix sort on MIC Architecture: …The MIC architecture is an x86-based many-core processor architecture based on small in-order cores that uniquely combines full programmability of today’s general-purpose CPU architectures with compute-throughput and memory bandwidth capabilities of modern GPU architectures. Each core is a general-purpose processor, which has a scalar unit based on the Pentium processor design, as well as a vector unit that supports 16 32-bit float or integer operations per clock. The MIC architecture has two levels of cache: low latency L1 cache and larger globally coherent L2 cache that is partitioned among the cores. Knights Ferry (KNF) (an implementation of the MIC architecture), has a 32 kB L1 cache and 256 kB partitioned L2 cache. To further hide latency, each core is augmented with 4-way multithreading."
- Gareth Halfacree (20 June 2011), "Intel pushes for HPC space with Knights Corner", www.thinq.co.uk (Net Communities Limited, UK)
- "Intel Many Integrated Core Architecture", www.many-core.group.cam.ac.uk (Intel), December 2010
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- Rick Merritt (20 June 2011), "OEMs show systems with Intel MIC chips", www.eetimes.com (EE Times)
- Efficient Hybrid Execution of C++ Applications using Intel(R) Xeon Phi(TM) Coprocessor, arXiv:1211.5530 [cs.DC], 23 November 2012
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- Jon Stokes (20 June 2011). "Intel takes wraps off 50-core supercomputing processor plans". Ars Technica.
- Hazra, Raj (18 June 2012), "Intel® Xeon® Phi™ coprocessors accelerate the pace of discovery and innovation", blogs.intel.com, "Today, with the announcement of Intel® Xeon® Phi™ coprocessors, we’re going to accelerate the pace of these discoveries and innovations. Intel® Xeon Phi products extend the Intel® Xeon® brand.."