|Design||manycore extended x86/x64 design|
|General purpose||Intel Architecture registers|
|Floating point||512-bit SIMD vector registers|
Intel Many Integrated Core Architecture or Intel MIC (pronounced Mike) is a multiprocessor computer architecture developed by Intel incorporating earlier work on the Larrabee many core architecture, the Teraflops Research Chip multicore chip research project, and the Intel Single-chip Cloud Computer multicore microprocessor.
Prototype products codenamed Knights Ferry were announced and released to developers in 2010. The Knights Corner product was announced in 2011 and uses a 22nm process. A second generation product codenamed Knights Landing using a 14nm process was announced in June 2013.
In September 2011, the Texas Advanced Computing Center (TACC) announced it would use Knights Corner cards in their 10 PetaFLOPS "Stampede" supercomputer, providing 8 PetaFLOPS of computing power.
In November 2012, Intel formally announced the first products citing claims of CPU-like versatile programmability, high performance and power efficiency. The Green 500 list placed a system using these new products as the most power efficient computer in the world.
In June 2013, the Tianhe-2 supercomputer at the National Supercomputing Center in Guangzhou (NSCC-GZ) was announced as the world's fastest supercomputer. It utilizes Intel Ivy Bridge-EP Xeon and Xeon Phi processors to achieve 33.86 PetaFLOPS.
The Larrabee microarchitecture (in development since 2006) introduced very wide (512-bit) SIMD units to a x86 architecture based processor design, extended to a cache coherent multiprocessor system connected via a ring bus to memory; each core was capable of 4-way multi-threading. Due to the design being intended for GPU as well as general purpose computing the Larrabee chips also included specialised hardware for texture sampling. The project to produce a GPU retail product directly from the Larrabee research project was terminated in May 2010.
Another contemporary Intel research project implementing x86 architecture on a many-multicore processor was the 'Single Chip Cloud Computer', (prototype introduced 2009.), a design mimicking a cloud computing computer datacentre on a single chip with multiple independent cores - the prototype design included 48 cores per chip with hardware support for selective frequency and voltage control of cores to maximize energy efficiency, and incorporated a mesh network for interchip messaging. The design lacked cache coherent cores and focused on principles that would allow the design to scale to many more cores.
The Teraflops Research Chip (prototype unveiled 2007) was an experimental 80 core chip with two floating point units per core implementing not x86 but a 96-bit VLIW architecture. The project investigated intercore communication methods, per-chip power management, and achieved 1.01 TFLOPS at 3.16 GHz consuming 62 W of power.
Intel's MIC prototype board, named Knights Ferry, incorporating a processor codenamed Aubrey Isle was announced 31 May 2010. The product was stated to be a derivative of the Larrabee project and other Intel research including the Single-chip Cloud Computer.
The development product was offered as a PCIe card with 32 in-order cores at up to 1.2 GHz with four threads per core, 2 GB GDDR5 memory, and 8 MB coherent L2 cache (256 kB per core with 32 kB L1 cache), and a power requirement of ~300 W, built at a 45 nm process. In the Aubrey Isle core a 1,024-bit ring bus (512-bit bi-directional) connects processors to main memory. Single board performance has exceeded 750 GFLOPS. The prototype boards only support single precision floating point instructions.
Initial developers included CERN, Korea Institute of Science and Technology Information (KISTI) and Leibniz Supercomputing Centre. Hardware vendors for prototype boards included IBM, SGI, HP, Dell and others.
In June 2011, SGI announced a partnership with Intel to utilize the MIC architecture in its high performance computing products. In September 2011, it was announced that the Texas Advanced Computing Center (TACC) will use Knights Corner cards in their 10 PetaFLOPS "Stampede" supercomputer, providing 8 PetaFLOPS of the compute power. According to "Stampede: A Comprehensive Petascale Computing Environment" the "second generation Intel (Knights Landing) MICs will be added when they become available, increasing Stampede's aggregate peak performance to at least 15 PetaFLOPS."
On June 5, 2012, Intel released open source software and documentation regarding Knights Corner.
In June 2012, ScaleMP announced it will provide its virtualization software to allows using 'Knight's Corner' chips (branded as 'Xeon Phi') as main processor transparent extension. The virtualization software will allow 'Knight's Corner' to run legacy MMX/SSE code and access unlimited amount of (host) memory without need for code changes.
Code name for the second generation MIC architecture product from Intel. Intel officially first revealed details of its second generation Intel Xeon Phi products on June 17, 2013. Intel said that the next generation of Intel MIC Architecture-based products will be available in two forms, as a coprocessor or a host processor (CPU), and be manufactured using Intel's 14nm process technology. Knights Landing products will include integrated on-package memory for significantly higher memory bandwidth.
Knights Landing will be built using up to 72 Airmont (Atom) cores with four threads per core, support for up to 384 GB of DDR4 RAM and 8–16 GB of stacked 3D MCDRAM. Each core will have two 512-bit vector units and will support AVX-512F (AVX3.1) SIMD instructions with Intel AVX-512 Conflict Detection Instructions (CDI), Intel AVX-512 Exponential and Reciprocal Instructions (ERI), and Intel AVX-512 Prefetch Instructions (PFI), along with Intel's full x86 instruction set except TSX. Knights Landing's TDP will range from 160 to 215 W.
On November 12, 2012, Intel announced two Xeon Phi coprocessor families which are the Xeon Phi 3100 and the Xeon Phi 5110P. The Xeon Phi 3100 will be capable of more than 1 teraflops of double precision floating point instructions with 240 GB/sec memory bandwidth at 300 W. The Xeon Phi 5110P will be capable of 1.01 teraflops of double precision floating point instructions with 320 GB/sec memory bandwidth at 225 W. The Xeon Phi 7120P will be capable of 1.2 teraflops of double precision floating point instructions with 352 GB/sec memory bandwidth at 300 W.
The Xeon Phi uses the 22 nm process size. The Xeon Phi 3100 will be priced at under US$2,000 while the Xeon Phi 5110P will have a price of US$2,649 and Xeon Phi 7120 at US$4129.00. On June 17, 2013, the Tianhe-2 supercomputer was announced by TOP500 as the world's fastest. It uses Intel Ivy Bridge Xeon and Xeon Phi processors to achieve 33.86 PetaFLOPS.
An empirical performance and programmability study has been performed by researchers. The authors claim that to achieve high performance Xeon Phi still needs help from programmers and that merely relying on compilers with traditional programming models is still far from reality.
The cores of Intel MIC are based on a modified version of P54C design, used in the original Pentium. The basis of the Intel MIC architecture is to leverage x86 legacy by creating a x86-compatible multiprocessor architecture that can utilize existing parallelization software tools. Programming tools include OpenMP, OpenCL, Cilk/Cilk Plus and specialised versions of Intel's Fortran, C++ and math libraries.
Design elements inherited from the Larrabee project include x86 ISA, 4-way SMT per core, 512-bit SIMD units, coherent L2 cache (512 KB per core), and ultra-wide ring bus connecting processors and memory.
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|Wikimedia Commons has media related to Xeon Phi.|
- Intel pages: Xeon Phi Product Family
- Hazra, Raj (18 June 2012), "Intel® Xeon® Phi™ coprocessors accelerate the pace of discovery and innovation", blogs.intel.com, "Today, with the announcement of Intel® Xeon® Phi™ coprocessors, we’re going to accelerate the pace of these discoveries and innovations. Intel® Xeon Phi products extend the Intel® Xeon® brand.."
- Intel teaches Xeon Phi x86 coprocessor snappy new tricks