x86 virtualization

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In computing, x86 virtualization refers to hardware virtualization for the x86 architecture. It allows multiple operating systems to simultaneously share x86 processor resources in a safe and efficient manner.

In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of virtualization support while attaining reasonable performance. In 2006, both Intel (VT-x) and AMD (AMD-V) introduced limited hardware virtualization support that allowed for simpler virtualization software but offered very little speed benefits.[1] Greater hardware support, that allowed for substantial speed improvements, came with later processor models.

Software-based virtualization[edit]

The following discussion focuses only on virtualization of protected mode of the x86 architecture.

In protected mode the operating system kernel runs at a higher privilege such as ring 0, and applications at a lower privilege such as ring 3. In software-based virtualization, a host OS has direct access to hardware while the guest OSs have limited access to hardware, just like any other application of the host OS. One approach used in x86 software-based virtualization to overcome this limitation is called ring deprivileging, in which involves running the guest OS at a ring higher than 0.[2]

Three techniques made virtualization of protected mode possible:

  • Binary translation is used to rewrite in terms of ring 3 instructions certain ring 0 instructions, such as POPF, that would otherwise fail silently or behave differently when executed above ring 0,[3][4]:3 making the classic trap-and-emulate virtualization impossible.[4]:1[5] To improve performance, the translated basic blocks need to be cached in a coherent way that detects code patching (used in VxDs for instance), the reuse of pages by the guest OS, or even self-modifying code.[6]
  • A number of key data structures used by a processor need to be shadowed. Because most operating systems use paged virtual memory, and granting the guest OS direct access to the MMU would mean loss of control by the virtualization manager, some of the work of the x86 MMU needs to be duplicated in software for the guest OS using a technique known as shadow page tables.[7]:5[4]:2 This involves denying the guest OS any access to the actual page table entries by trapping access attempts and emulating them instead in software. The x86 architecture uses hidden state to store segment descriptors in the processor, so once the segment descriptors have been loaded into the processor, the memory from which they have been loaded may be overwritten and there is no way to get the descriptors back from the processor. Shadow descriptor tables must therefore be used to track changes made to the descriptor tables by the guest OS.[5]
  • I/O device emulation: Unsupported devices on the guest OS must be emulated by a device emulator that runs in the host OS.[8]

These techniques incur some performance overhead due to lack of MMU virtualization support, as compared to a VM running on a natively virtualizable architecture such as the IBM System/370.[4]:10[9]:17 and 21

On traditional mainframes, the classic type 1 hypervisor was self-standing and did not depend on any operating system or run any user applications itself. In contrast, the first x86 virtualization products were aimed at workstation computers, and ran a guest OS inside a host OS by embedding the hypervisor in a kernel module that ran under the host OS (type 2 hypervisor).[8]

There has been some controversy whether the x86 architecture with no hardware assistance is virtualizable as described by Popek and Goldberg. VMware researchers pointed out in a 2006 ASPLOS paper that the above techniques made the x86 platform virtualizable in the sense of meeting the three criteria of Popek and Goldberg, albeit not by the classic trap-and-emulate technique.[4]:2–3

A different route was taken by other systems like Denali, L4, and Xen, known as paravirtualization, which involves porting operating systems to run on the resulting virtual machine, which does not implement the parts of the actual x86 instruction set that are hard to virtualize. The paravirtualized I/O has significant performance benefits as demonstrated in the original SOSP'03 Xen paper.[10]

The initial version of x86-64 (AMD64) did not allow for a software-only full virtualization due to the lack of segmentation support in long mode, which made the protection of the hypervisor's memory impossible, in particular, the protection of the trap handler that runs in the guest kernel address space.[11][12]:11 and 20 Revision D and later 64-bit AMD processors (as a rule of thumb, those manufactured in 90 nm or less) added basic support for segmentation in long mode, making it possible to run 64-bit guests in 64-bit hosts via binary translation. Intel did not add segmentation support to its x86-64 implementation (Intel 64), making 64-bit software-only virtualization impossible on Intel CPUs, but Intel VT-x support makes 64-bit hardware assisted virtualization possible on the Intel platform.[13][14]:4

On some platforms, it is possible to run a 64-bit guest on a 32-bit host OS if the underlying processor is 64-bit and supports the necessary virtualization extensions.

Hardware-assisted virtualization[edit]

In 2005 and 2006, Intel and AMD (working independently) created new processor extensions to the x86 architecture. The first generation of x86 hardware virtualization addressed the issue of privileged instructions. The issue of low performance of virtualized system memory was addressed with MMU virtualization that was added to the chipset later.

Processor[edit]

Virtual 8086 mode[edit]

Based on painful experiences with the 80286 protected mode, which by itself was not suitable enough to run well concurrent MS-DOS applications, Intel introduced the virtual 8086 mode in their 80386 chip, which offered virtualized 8086 processors on the 386 and later chips. Hardware support for virtualizing the protected mode itself, however, became available 20 years later.[15]

AMD virtualization (AMD-V) [edit]

AMD developed its first generation virtualization extensions under the code name "Pacifica", and initially published them as AMD Secure Virtual Machine (SVM),[16] but later marketed them under the trademark AMD Virtualization, abbreviated AMD-V.

On May 23, 2006, AMD released the Athlon 64 ("Orleans"), the Athlon 64 X2 ("Windsor") and the Athlon 64 FX ("Windsor") as the first AMD processors to support this technology.

AMD-V capability also features on the Athlon 64 and Athlon 64 X2 family of processors with revisions "F" or "G" on socket AM2, Turion 64 X2, and Opteron 2nd generation[17] and 3rd-generation,[18] Phenom and Phenom II processors. The APU Fusion processors support AMD-V. AMD-V is not supported by any Socket 939 processors. The only Sempron processors which support it are Huron and Sargas.

AMD Opteron CPUs beginning with the Family 0x10 Barcelona line, and Phenom II CPUs, support a second generation hardware virtualization technology called Rapid Virtualization Indexing (formerly known as Nested Page Tables during its development), later adopted by Intel as Extended Page Tables (EPT).

The CPU flag for AMD-V is "svm". This may be checked in BSD derivatives via dmesg or sysctl and in Linux via /proc/cpuinfo.[19]

Intel virtualization (VT-x)[edit]

Intel Core i7 (Bloomfield) CPU

Previously codenamed "Vanderpool", VT-x represents Intel's technology for virtualization on the x86 platform. On November 13, 2005, Intel released two models of Pentium 4 (Model 662 and 672) as the first Intel processors to support VT-x. The CPU flag for VT-x is "vmx"; in Linux, this may be checked via /proc/cpuinfo, or in Mac OS X via sysctl machdep.cpu.features.[19]

As of 2009 not all Intel processors supported VT-x, which Intel uses to segment its market.[20] Support for VT-x may even vary between different versions (as identified by Intel's sSpec Number) of the same model number.[21][22] For a complete and up-to-date list see the Intel website.[23] Even in May, 2011, the Intel CPU P6100 which is used in laptops does not support hardware virtualization.[24]

With some motherboards, Intel's VT-x feature must be enabled in the BIOS before applications can make use of it.[25]

Intel started to include Extended Page Tables (EPT),[26] a technology for page-table virtualization,[27] since the Nehalem architecture.[28][29] Westmere added support for launching the logical processor directly in real mode—a feature called "unrestricted guest", and which requires EPT to work.[30][31]

Intel started to include VMCS Shadowing, a technology to accelerate nested virtualization of VMMs, since the Haswell architecture.[32]

VIA virtualization (VIA VT)[edit]

VIA Nano 3000 Series Processors[33] and higher support a so-called VIA VT virtualization technology compatible with Intel VT.

Software using AMD-V or Intel VT[edit]

Chipset[edit]

Memory and I/O virtualization is performed by the chipset.[34] Typically these features must be enabled by the BIOS, which must be able to support them and also be set to use them.

I/O MMU virtualization (AMD-Vi and VT-d)[edit]

An input/output memory management unit (IOMMU) enables guest virtual machines to directly use peripheral devices, such as Ethernet, accelerated graphics cards, and hard-drive controllers, through DMA and interrupt remapping. This is sometimes called PCI passthrough.[35] Both AMD and Intel have released specifications:

  • AMD's I/O Virtualization Technology, "AMD-Vi", originally called "IOMMU".[36]
  • Intel's "Virtualization Technology for Directed I/O" (VT-d),[37] included in most high-end (but not all) Nehalem and newer Intel processors.[38]

In addition to the CPU support, both motherboard chipset and system firmware (BIOS or UEFI) need to fully support the IOMMU I/O virtualization functionality in order for it to be actually usable. Only the PCI or PCI Express devices supporting function level reset (FLR) can be virtualized this way, as it is required for reassigning various device functions between virtual machines.[39][40]

Network virtualization (VT-c)[edit]

  • Intel's "Virtualization Technology for Connectivity" (VT-c).[41]
Virtual Machine Device Queues (VMDQ)[edit]
PCI-SIG Single Root I/O Virtualization (SR-IOV)[edit]

PCI-SIG Single Root I/O Virtualization (SR-IOV) provides a set of general (non-x86 specific) I/O virtualization methods based on PCI Express (PCIe) native hardware, as standardized by PCI-SIG:[42]

  • Address translation services (ATS) supports native IOV across PCI Express via address translation. It requires support for new transactions to configure such translations.
  • Single-root IOV (SR-IOV or SRIOV) supports native IOV in existing single-root complex PCI Express topologies. It requires support for new device capabilities to configure multiple virtualized configuration spaces.
  • Multi-root IOV (MR-IOV) supports native IOV in new topologies (for example, blade servers) by building on SR-IOV to provide multiple root complexes which share a common PCI Express hierarchy.

In SR-IOV, the most common of these, a host VMM configures supported devices to create and allocate virtual "shadows" of their configuration spaces so that virtual machine guests can directly configure and access such "shadow" device resources.[43] With SR-IOV enabled, virtualized network interfaces are able to achieve over 95% of the bare metal network bandwidth in NASA's virtualized datacenter[44] and in the Amazon Public Cloud.[45][46]

See also[edit]

References[edit]

  1. ^ A Comparison of Software and Hardware Techniques for x86 Virtualization, Keith Adams and Ole Agesen, VMware, ASPLOS’06 October 21–25, 2006, San Jose, California, USA"Surprisingly, we find that the first-generation hardware support rarely offers performance advantages over existing software techniques. We ascribe this situation to high VMM/guest transition costs and a rigid programming model that leaves little room for software flexibility in managing either the frequency or cost of these transitions.
  2. ^ "Intel Virtualization Technology: Hardware Support for Efficient Processor Virtualization". Intel.com. 2006-08-10. Retrieved 2010-05-02. 
  3. ^ "USENIX Technical Program - Abstract - Security Symposium - 2000". Usenix.org. 2002-01-29. Retrieved 2010-05-02. 
  4. ^ a b c d e "A Comparison of Software and Hardware Techniques for x86 Virtualization" (PDF). VMware. Retrieved 8 September 2010. 
  5. ^ a b U.S. Patent 6,397,242
  6. ^ U.S. Patent 6,704,925
  7. ^ "Virtualization: architectural considerations and other evaluation criteria" (PDF). VMware. Retrieved 8 September 2010. 
  8. ^ a b U.S. Patent 6,496,847
  9. ^ "VMware and Hardware Assist Technology" (PDF). Retrieved 2010-09-08. 
  10. ^ "Xen and the Art of Virtualization" (PDF). 
  11. ^ "How retiring segmentation in AMD64 long mode broke VMware". Pagetable.com. 2006-11-09. Retrieved 2010-05-02. 
  12. ^ "VMware and CPU Virtualization Technology" (PDF). VMware. Retrieved 2010-09-08. 
  13. ^ "VMware KB: Hardware and firmware requirements for 64bit guest operating systems". Kb.vmware.com. Retrieved 2010-05-02. 
  14. ^ "Software and Hardware Techniques for x86 Virtualization" (PDF). Retrieved 2010-05-02. 
  15. ^ Yager, Tom (2004-11-05). "Sending software to do hardware's job | Hardware - InfoWorld". Images.infoworld.com. Retrieved 2014-01-08. 
  16. ^ "33047_SecureVirtualMachineManual_3-0.book" (PDF). Retrieved 2010-05-02. 
  17. ^ "What are the main differences between Second-Generation AMD Opteron processors and first-generation AMD Opteron processors? publisher=Amd.com". Retrieved 2012-02-04. [dead link]
  18. ^ "What virtualization enhancements do Third-Generation AMD Opteron processors feature?". Amd.com. Retrieved 2012-02-04. [dead link]
  19. ^ a b To see if your processor supports hardware virtualization Intel 2012.
  20. ^ Stokes, Jon (2009-05-08). "Microsoft, Intel goof up Windows 7's "XP Mode"". Arstechnica.com. Retrieved 2010-05-02. 
  21. ^ "Processor Spec Finder". Processorfinder.intel.com. Retrieved 2010-05-02. 
  22. ^ "Intel Processor Number Details". Intel. Intel. 2007-12-03. Retrieved 2008-10-03. 
  23. ^ "Intel Virtualization Technology List". Ark.intel.com. Retrieved 2010-05-02. 
  24. ^ "Intel Pentium P6100 (3M cache, 2.00 GHz)". Ark.intel.com. Retrieved 2012-02-04. 
  25. ^ "Windows Virtual PC: Configure BIOS". Microsoft. Retrieved 2010-09-08. 
  26. ^ Neiger, Gil; A. Santoni, F. Leung, D. Rodgers, R. Uhlig. "Intel Virtualization Technology: Hardware Support for Efficient Processor Virtualization". Intel Technology Journal (Intel) 10 (3): 167–178. doi:10.1535/itj.1003.01. Retrieved 2008-07-06. 
  27. ^ Gillespie, Matt (2007-11-12). "Best Practices for Paravirtualization Enhancements from Intel Virtualization Technology: EPT and VT-d". Intel Software Network. Intel. Retrieved 2008-07-06. 
  28. ^ "First the Tick, Now the Tock: Next Generation Intel Microarchitecture (Nehalem)" (PDF) (Press release). Intel. Retrieved 2008-07-06. 
  29. ^ "Technology Brief: Intel Microarchitecture Nehalem Virtualization Technology" (PDF). Intel. 2009-03-25. Retrieved 2009-11-03. 
  30. ^ http://2013.asiabsdcon.org/papers/abc2013-P5A-paper.pdf: "Intel added unrestricted guest mode on Westmere micro-architecture and later Intel CPUs, it uses EPT to translate guest physical address access to host physical address. With this mode, VMEnter without enable paging is allowed."
  31. ^ http://download.intel.com/products/processor/manual/326019.pdf: "If the “unrestricted guest” VM-execution control is 1, the “enable EPT” VM-execution control must also be 1"
  32. ^ "4th Gen Intel Core vPro Processors with Intel VMCS Shadowing" (PDF) (Press release). Intel. Retrieved 2013-08-17. 
  33. ^ VIA Introduces New VIA Nano 3000 Series Processors
  34. ^ "Intel platform hardware support for I/O virtualization". Intel.com. 2006-08-10. Retrieved 2012-02-04. 
  35. ^ "Linux virtualization and PCI passthrough". IBM. Retrieved 10 November 2010. 
  36. ^ "AMD I/O Virtualization Technology (IOMMU) Specification Revision 1.26". Retrieved 2011-05-24. 
  37. ^ "Intel Virtualization Technology for Directed I/O (VT-d) Architecture Specification" (PDF). Retrieved 2012-02-04. 
  38. ^ "Intel Virtualization Technology for Directed I/O (VT-d) Supported CPU List". Ark.intel.com. Retrieved 2012-02-04. 
  39. ^ "Function Level Reset (FLR)". PCI-SIG Engineering Change Notice. pcisig.com. 2006-06-27. Retrieved 2014-01-10. 
  40. ^ "Xen VT-d". xen.org. 2013-06-06. Retrieved 2014-01-10. 
  41. ^ "Intel Virtualization Technology for Connectivity (VT-c)". Intel.com. Retrieved 2012-02-04. 
  42. ^ "PCI-SIG I/O Virtualization (IOV) Specifications". Pcisig.com. 2011-03-31. Retrieved 2012-02-04. 
  43. ^ Yaozu Dong, Zhao Yu, Greg Rose (2008). "SR-IOV Networking in Xen: Architecture, Design and Implementation". usenix.org. USENIX. Retrieved 2014-01-10. 
  44. ^ "NASA’s Flexible Cloud Fabric: Moving Cluster Applications to the Cloud". Intel. Retrieved 2014-01-08. 
  45. ^ "Enhanced Networking in the AWS Cloud". Scalable Logic. 2013-12-31. Retrieved 2014-01-08. 
  46. ^ "Enhanced Networking in the AWS Cloud - Part 2". Scalable Logic. 2013-12-31. Retrieved 2014-01-08. 

External links[edit]