Intel i960HA microprocessor
|Produced||From 1984 to 2007|
|Max. CPU clock rate||10 MHz to 100 MHz|
Intel's i960 (or 80960) was a RISC-based microprocessor design that became popular during the early 1990s as an embedded microcontroller, becoming a best-selling CPU in that field, along with the competing AMD 29000. In spite of its success, Intel dropped i960 marketing in the late 1990s as a side effect of a settlement with DEC in which Intel received the rights to produce the StrongARM CPU. The processor continues to be used in a few military applications.
The i960 design was started as a response to the failure of Intel's iAPX 432 design of the early 1980s. The iAPX 432 was intended to directly support high-level languages that supported tagged, protected, garbage-collected memory — such as Ada and Lisp — in hardware. Because of its instruction-set complexity, its multi-chip implementation, and design flaws, the iAPX 432 was very slow in comparison to other processors of its time.
In 1984 Intel and Siemens started a joint project, ultimately called BiiN, to create a high-end fault-tolerant object-oriented computer system programmed entirely in Ada. Many of the original i432 team members joined this project, though a new lead architect, Glenford Myers, was brought in from IBM. The intended market for the BiiN systems were high-reliability computer users such as banks, industrial systems and nuclear power plants.
Intel's major contribution to the BiiN system was a new processor design, influenced by the protected-memory concepts from the i432. The new design included a number of features to improve performance and avoid problems that had led to the downfall of the i432, which resulted in the i960 design. The first 960 processors entered the final stages of design, known as taping-out, in October 1985 and were sent to manufacturing that month, with the first working chips arriving in late 1985 and early 1986.
The BiiN effort eventually failed, due to market forces, and the 960MX was left without a use. Myers attempted to save the design by outlining several subsets of the full capability architecture created for the BiiN system. He tried to convince Intel management to market the i960 (then still known as the "P7") as a general-purpose processor, both in place of the Intel 80286 and i386 (which taped-out the same month as the first i960), as well as the emerging RISC market for Unix systems, including a pitch to Steve Jobs for use in the NeXT system. Competition within and outside of Intel came not only from the i386 camp, but also from the i860 processor, yet another RISC processor design emerging within Intel at the time. Myers was unsuccessful at convincing Intel management to support the i960 as a general-purpose or Unix processor, but the chip found a ready market in early high-performance 32-bit embedded systems.
To avoid the performance issues that plagued the i432, the central i960 instruction-set architecture was a RISC design, only implemented in full in the i960MX, and the memory subsystem was made 33-bits wide — for a 32-bit word and a "tag" bit to indicate protected memory. In many other ways the i960 followed the original Berkeley RISC design, notably in its use of register windows, an implementation-specific number of caches for the per-subroutine registers, allowing for fast routine calls. The competing Stanford University design, commercialized as MIPS, did not use this system, relying on the compiler to generate optimal subroutine call and return code instead. In common with most 32-bit designs, the i960 has a flat 32-bit memory space, with no memory segmentation. The i960 architecture also anticipated a superscalar implementation, with instructions being simultaneously dispatched to more than one unit within the processor.
The "full" i960MX was never released for the non-military market, but the otherwise identical i960MC was used in high-end embedded applications. The i960MC included all of the features of the original BiiN system, but these were simply not mentioned in the literature, leading many to wonder why the i960MC was so large and had so many pins labeled "no connect".
A version of the RISC core without memory management or an FPU became the i960KA, and the RISC core with the FPU became the i960KB. The versions were, however, all identical internally — only the labeling was different. This meant the CPUs were much larger than necessary for the "actually supported" feature sets, and as a result, more expensive to manufacture than they needed to be.
The i960KA became successful as a low-cost 32-bit processor for the laser-printer market, as well as for early graphics terminals and other embedded applications. Its success paid for future generations, which removed the complex memory sub-system.
The i960CA, first announced in July 1989, was the first pure RISC implementation of the i960 architecture. It featured a newly designed superscalar RISC core and added an unusual addressable on-chip cache, but lacked an FPU and MMU, as it was intended for high-performance embedded applications. The i960CA is widely considered to have been the first single-chip superscalar RISC implementation. The C-series only included one ALU, but could dispatch and execute an arithmetic instruction, a memory reference, and a branch instruction at the same time, and sustain two instructions per cycle under certain circumstances. The first versions released ran at 33 MHz, and Intel promoted the chip as capable of 66 MIPS. The i960CA microarchitecture was designed in 1987–1988 and formally announced on September 12, 1989. Later, the i960CF included a floating-point unit, but continued to omit an MMU.
The 80960Jx is a processor for embedded applications. It features 32-bit multiplexed address/data bus, instruction and data cache, 1K on-chip RAM, interrupt controller and two independent 32-bit timers. The 80960Jx’s testability features included ONCE (on-circuit emulation) mode and boundary scan (JTAG).
Announced October 1998 i960VH Embedded-PCI processor featured 32-bit 33 MHz PCI bus and 100 MHz i960JT processor core. The core also featured 16 KB of instruction cache, 4 KB of data cache and 1 KB of built-in RAM. Other core features included two 32-bit timers, programmable interrupt controller, I²C interface and a two-channel DMA controller.
Intel attempted to bolster the i960 in the I/O device controller market with the I2O standard, but this had little success and the design work was eventually ended. By the mid 1990s its price/performance ratio had fallen behind competing chips of more recent design, and Intel never produced a reduced power-consumption version that could be used in battery-powered systems.
In 1990 the i960 team was redirected to be the "second team" working in parallel on future i386 implementations — specifically the P6 processor, which later became the Pentium Pro. The i960 project was sent to another, smaller development team, essentially ensuring its ultimate demise.
Because of its high performance in calculating XOR values, the Intel 960 processor family is often used to control higher-end, RAID-capable SCSI disk array host adapter cards as well as Digital Equipment/Compaq/HP's high-end SCSI and DSSI and eventually Fibre Channel HSx series standalone RAID controllers 
An i960RS chip also powers Adaptec's AAR-2400A controller, which uses four commodity parallel ATA drives to build an affordable RAID-5 protected fault-tolerant storage system for small PC servers and workstations.
The Intel 960 architecture is also used in slot machines. Currently they are found in IGT's Stepper S2000 family and i960 video family. It was also used as the main CPU of Sega's famous Model 2 series of arcade boards.
The Indian Space Research Organisation (ISRO) is said to use the chip in its on-board computers in its launch vehicles.
It was also used on some HP X-Terminals.
- i960 homepage at Intel
- i960 images and descriptions at cpu-collection.de
- Intel i960 ID Guide
- BiiN CPU Architecture Reference Manual (describes i960MX instruction set), authored by Randal L. Schwartz
- "Intel cashes in ancient chips".
- http://www.dectrader.com/on_platform-storageworks-seminar-by-kevin-schumacher-mark-difabio-op.html On Platform Storageworks Seminar notes