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|Institutions||currently Intel, formerly Compaq and Digital Equipment Corporation|
|Alma mater||Purdue University
University of Illinois, Urbana-Champaign
|Doctoral advisor||Edward S. Davidson|
|Known for||quantitative approach to processor evaluation, contributions to micro-architecture, Asim simulator|
|Notable awards||Eckert–Mauchly Award, IEEE Fellow, ACM Fellow|
Dr Joel Emer is a pioneer in computer performance analysis techniques and a microprocessor architect. He is currently an Intel Fellow. He was the 2009 recipient of the Eckert–Mauchly Award, an ACM/IEEE joint award for contributions to computer and digital systems architecture. Dr Emer received his Ph.D. degree from the University of Illinois, Urbana-Champaign under the supervision of Prof. Edward S. Davidson. His first job immediately after graduation was at Digital Equipment Corporation where he initially worked on VAX performance evaluation and then on Alpha performance evaluation. As a consequence of his performance evaluation work, he became a pioneer in the quantitative approach to computer architecture. In conjunction with the development and application of various performance analysis techniques, he contributed a variety of research and advanced development ideas that were incorporated into various VAX and Alpha designs.
He is well known, along with his co-author Douglas W. Clark, for a seminal paper on the quantitative analysis[disambiguation needed] of processor architectures, which was published in the 11th International Symposium on Computer Architecture. That paper also contained the result that the VAX-11/780's performance was actually 0.5 MIPS instead of 1 MIPS as was previously claimed by DEC. That result helped popularize what Clark called the Iron Law of Performance that related cycles per instruction (CPI), frequency and number of instructions to computer performance.
- Emer, Joel S.; Clark, Douglas W. (1984). "A characterization of processor performance in the VAX-11/780". Proceedings of the 11th Annual International Symposium on Computer Architecture. pp. 301–310.