- This article is about the heuristic algorithm for the graph partitioning problem. For a heuristic for the traveling salesperson problem, see Lin–Kernighan heuristic.
Kernighan–Lin is a O(n2 log(n)) heuristic algorithm for solving the graph partitioning problem. The algorithm has important applications in the layout of digital circuits and components in VLSI.
Let be a graph, and let be the set of nodes and the set of edges. The algorithm attempts to find a partition of into two disjoint subsets and of equal size, such that the sum of the weights of the edges between nodes in and is minimized. Let be the internal cost of a, that is, the sum of the costs of edges between a and other nodes in A, and let be the external cost of a, that is, the sum of the costs of edges between a and nodes in B. Furthermore, let
be the difference between the external and internal costs of a. If a and b are interchanged, then the reduction in cost is
where is the cost of the possible edge between a and b.
The algorithm attempts to find an optimal series of interchange operations between elements of and which maximizes and then executes the operations, producing a partition of the graph to A and B.
1 function Kernighan-Lin(G(V,E)): 2 determine a balanced initial partition of the nodes into sets A and B 3 A1 := A; B1 := B 4 do 5 compute D values for all a in A1 and b in B1 6 for (n := 1 to |V|/2) 7 find a[i] from A1 and b[j] from B1, such that g[n] = D[a[i]] + D[b[j]] - 2*c[a[i]][b[j]] is maximal 8 move a[i] to B1 and b[j] to A1 9 remove a[i] and b[j] from further consideration in this pass 10 update D values for the elements of A1 = A1 \ a[i] and B1 = B1 \ b[j] 11 end for 12 find k which maximizes g_max, the sum of g,...,g[k] 13 if (g_max > 0) then 14 Exchange a,a,...,a[k] with b,b,...,b[k] 15 until (g_max <= 0) 16 return G(V,E)
- Kernighan, B. W.; Lin, Shen (1970). "An efficient heuristic procedure for partitioning graphs". Bell System Technical Journal 49: 291–307. doi:10.1002/j.1538-7305.1970.tb01770.x.
- Ravikumār, Si. Pi; Ravikumar, C.P (1995). Parallel methods for VLSI layout design. Greenwood Publishing Group. p. 73. ISBN 978-0-89391-828-6. OCLC 2009-06-12.