Link register

From Wikipedia, the free encyclopedia
Jump to: navigation, search

A link register, in many instruction set architectures such as the PowerPC, ARM, and the PA-RISC, is a special purpose register which holds the address to return to when a function call completes. Other architectures (such as SPARC) have a register with the same purpose but another name (in this case, "output register 7" or o7). [1] The usage of a link register allows for faster calls to leaf subroutines. When the subroutine is non-leaf, passing the result address in a register still results in generation of more efficient code for thunks, e.g. for a function whose sole purpose is to call another function with arguments rearranged in some way. Other subroutines can benefit from the use of link register because it can be saved in a batch with other callee-used registers—e.g. an ARM subroutine pushes registers 4-7 along with the link register, LR, by the single instruction STMDB SP!, {R4-R7, LR} pipelining all memory writes required.

References[edit]

  1. ^ "RTEMS SPARC Applications Supplement". May 2000. Retrieved 2013-04-19.