|Original author(s)||Ronald G. Minnich, Eric Biederman, Olli Lo, Stefan Reinauer, the coreboot community|
|Stable release||Rolling release|
|Written in||Mostly C, only about 1% ASM|
|Platform||x86 x86-64, ARMv7|
coreboot (formerly known as LinuxBIOS) is a free software project, endorsed by the Free Software Foundation, aimed at replacing the proprietary BIOS firmware found in most computers with a lightweight system designed to perform only the minimum of tasks necessary to load and run a modern 32-bit or 64-bit operating system.
The coreboot project began in the winter of 1999 in the Advanced Computing Laboratory at Los Alamos National Laboratory (LANL). The goal was a BIOS that would start fast and handle errors intelligently. It is licensed under the terms of the GNU General Public License (GPL). Main contributors have been LANL, AMD, coresystems GmbH and Linux Networx, Inc, as well as motherboard vendors MSI, Gigabyte, and Tyan, by offering coreboot next to their standard BIOS or providing specifications of the hardware interfaces for some of their recent motherboards. However, Tyan seems to have ceased support of coreboot. Google partly sponsors the coreboot project. CME Group, a cluster of futures exchanges, began supporting the coreboot project in 2009.
Besides x86 and x86-64 architectures, coreboot support also exists for the AMD Geode solutions. Support started with the Geode GX processor developed by AMD for the OLPC, Artec Group then added Geode LX support for its model DBE61 ThinCan. Recently, that code was adopted by AMD and further polished for the OLPC after they upgraded to the Geode LX platform. That code is now being further developed by the coreboot community to support other AMD Geode solutions. Coreboot can be flashed onto an AMD Geode platform using Flashrom.
From that initial development on AMD Geode based platforms, coreboot support has been extended onto many AMD processors and chipsets. The processor list includes Family 0Fh and 10h (K8 core), and recently Family 14h (Bobcat core, Fusion APU). Coreboot support also extends to AMD chipsets: RS690, RS7xx, SB600, and SB8xx.
AMD Generic Encapsulated Software Architecture (AGESA)—a bootstrap protocol by which system devices on AMD64 mainboards are initialized—was open sourced in early 2011, aiming to provide required functionality for coreboot system initialization on AMD64 hardware.
Coreboot typically loads a Linux kernel, but it can load any other stand-alone ELF executable, such as iPXE/gPXE/Etherboot, which can boot Linux over a network, or SeaBIOS, which can load Linux, Microsoft Windows 2000 and later, and *BSD (previously, Windows 2000/XP and OpenBSD support was provided by ADLO). Coreboot can also load almost any operating system from any supported device, such as Myrinet, Quadrics, or SCI cluster interconnects. Some OSes (such as Windows 2000/XP/Vista/7 and *BSD) require legacy BIOS functions which are provided by SeaBIOS.
A feature of coreboot is that the x86 version runs in 32-bit mode after executing only ten instructions (almost all other x86 BIOSes run exclusively in 16-bit mode). This is similar to the modern UEFI firmware, which is used on newer PC hardware.
Coreboot can boot other kernels, or pass control to a boot loader to boot a kernel/image instead. It can also boot a Plan 9 from Bell Labs kernel directly[clarification needed]. A coreboot-capable version of GNU GRUB 2 exists.
By default, coreboot does not provide BIOS call services. A payload called SeaBIOS can be used to provide BIOS calls and thus allow coreboot to load operating systems that require those services, however most modern operating systems access hardware in another manner and only use BIOS calls during early initialization and as a fallback mechanism.
Coreboot is written to perform the absolute minimal hardware initialization and then pass control to the operating system. Coreboot is:
- Simple: coreboot is written in C (except for a dozen lines of code in assembly language), has no user interface and does not require device drivers.
- Secure: no coreboot code is running once the operating system has taken control (on x86 or x86-64 CPUs, in particular, System Management Mode (SMM) is not activated). The C programming language was deliberately chosen to facilitate code audits.
- Suitable for real-time computing: by guaranteeing that System Management Mode (SMM) is not activated (and therefore that no code is running in SMM, a possible cause of latency), coreboot is compatible with real-time operating systems.
- Free and open-source: the entire source-code is available under the GNU GPL version 2, a strong copyleft license.
- Bootblock stage: prepare to obtain Flash access and look up the ROM stage to use
- ROM stage: memory and early chipset init (a bit like PEI in EFI)
- RAM stage: device enumeration and resource assignment, ACPI table creation, SMM handler (a bit like DXE stage in EFI)
The most difficult hardware that coreboot initializes is the DRAM controllers and DRAM. In some cases, technical documentation on this subject is NDA restricted or unavailable. RAM initialization is particularly difficult because before the RAM is initialized it cannot be used. Therefore, to initialize DRAM controllers and DRAM, the initialization code may have only the CPU's general purpose registers or Cache-as-RAM as temporary storage.
With newer x86 processors, the processor cache can be used as RAM until DRAM is initialized. The processor cache has to be initialized into Cache-as-RAM mode as well, but this needs fewer instructions than initializing DRAM. Also, the Cache-as-RAM mode initialization is specific to CPU architectures, thus more generic than DRAM initialization, which is specific to each chipset and mainboard.
Developing and debugging coreboot
Since coreboot must initialize the bare hardware, it must be ported to every chipset and motherboard that it supports. Before initializing RAM, coreboot initializes the serial port (addressing cache and registers only), so it can send out debug text to a connected terminal. It can also send byte codes to port 0x80 that are displayed on a two-hex-digit display of a connected POST card.
Another porting aid is the commercial "RD1 BIOS Savior" product from IOSS, which is a combination of two boot memory devices that plugs into the boot memory socket and has a manual switch to select between the two devices. The computer can boot from one device, and then the switch can be toggled to allow the computer to reprogram or "flash" the second device. A more expensive alternative is an external EPROM/flash programmer.
There are also CPU emulators that either replace the CPU or connect via a JTAG port, with the Sage SmartProbe being an example. Code can be built on, or downloaded to, BIOS emulators rather than flashing the BIOS device.
Coreboot can load a payload. Payloads can be written using the libpayload helper-library, but it is not required. Existing payloads include:
- SeaBIOS, a tiny implementation of x86 BIOS, written mostly in 16-bit C using the GNU C compiler. It is able to boot traditional PC operating systems.
- TianoCore, a free and open-source implementation of UEFI.
- OpenBIOS, a free and open-source implementation of Open Firmware.
- GNU GRUB, a bootloader
- FILO, a GRUB-like bootloader with USB boot support.
- Etherboot, it can boot an operating system over the network
- gPXE/iPXE, the successor to Etherboot, works when run under SeaBIOS.
- A branch of Das U-Boot used by Google for Chromium OS
- "Coreboot ARM". coreboot. 2013-10-15. Retrieved 2014-02-01.
- "[LinuxBIOS] Welcome to coreboot". 2008-01-12.
- The Free Software Foundation's Campaign for Free BIOS
- coreboot FAQ: Who is working on coreboot?
- Anton Borisov: The Open Source BIOS is Ten. An interview with the coreboot developers. The H, 2009.
- Google Sponsors the LinuxBIOS project
- CME Group Dives Into Coreboot
- "GSoC2011(Week 1): Analysis of U-boot ARM boot code | coreboot developer blogs". Retrieved 2014-04-12.
- "Coreboot GSoC". coreboot.org. Retrieved 2014-02-01.
- "Previous GSoC Projects". coreboot.org. Retrieved 2014-02-01.
- "Chromebooks". coreboot. 2014-01-16. Retrieved 2014-02-17.
- "Technical details on AMD's coreboot source code release". AMD. 2011-02-28. Retrieved 2014-07-02.
- SeaBIOS (previously known as LegacyBIOS) is an open-source legacy BIOS implementation
- coreboot Add-on Layer (ADLO)
- SEBOS, Security Enhanced Bootloader for Operating Systems, Phase 2 , adding PC BIOS Services to coreboot via Bochs BIOS (Link noted to be defunct on 18 July 2008. See SEBOS Phase 2 at the Wayback Machine (archived June 19, 2007))
- coreboot v3 early startup code
- Carl-Daniel Hailfinger. "On Coreboot". FOSDEM2012.
- Yinghai Lu; Li-Ta Lo; Gregory R. Watson; Ronald G. Minnich (2009-01-15). "CAR: Using Cache as RAM in Linux BIOS" (PDF). qmqm.pl. Retrieved 2014-02-25.
- A Framework for Using Processor Cache as RAM (CAR)
- Sage Engineering
- Google Pushes "Project PIANO" Into Coreboot
- "Modify u-boot code to allow building coreboot payload. [chromiumos/third_party/u-boot-next : chromeos-v2011.03]". 2011-07-24.
- Open BIOSes for Linux, by Peter Seebach
- LinuxBIOS ready to go mainstream, by Bruce Byfield
- First desktop motherboard supported by LinuxBIOS: GIGABYTE M57SLI-S4, by Brandon Howard
- Video recording of Ron Minnich's LinuxBIOS talk from FOSDEM 2007
- Coreboot Your Service, Linux Journal, October 2009