List of AMD CPU microarchitectures

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The following is a list of AMD CPU microarchitectures.


x86 microarchitectures[edit]

  • AMD K5 - AMD's first original microarchitecture. The K5 was based on the AMD Am29000 micro architecture with the addition of an x86 decoder. Although the design was similar in idea to a Pentium Pro, the actual performance was more like that of a Pentium.
  • AMD K6 - The K6 was not based on the K5 and was instead based on the Nx686 processor that was being designed by NexGen when that company was bought by AMD. The K6 was generally pin-compatible with the Intel Pentium (unlike NexGen's existing processors).
  • AMD K6-2 - An improved K6 with the addition of the 3DNow! SIMD instructions.
  • AMD K6-III - A further improved K6 with three levels of cache – 64 KB L1, 256 KB full-speed on-die L2, and a variable (up to 2 MB) L3.
  • AMD K7 Athlon - Microarchitecture of the AMD Athlon and Athlon XP microprocessors. Was a very advanced design for its day.
  • AMD K8 Hammer - Also called SledgeHammer, the K8s central processor unit is based on the K7 but was extended to 64 bits, added an integrated memory controller, HyperTransport communication fabric, L2 cache sizes up to 1 MB (1128 KB total cache), and SSE2. Later K8 added SSE3. The K8 was the first mainstream Windows-compatible 64-bit microprocessor and was released April 22, 2003. K8 replaced the traditional front side bus with a HyperTransport communication fabric. Also known as AMD Family 15.
  • AMD K10 Barcelona Family 10h microarchitecture - The Family 10h microarchitecture, called K10 popularly, is an architecture which is based on the K8 microarchitecture. Shared Level 3 Cache, 128-bit floating point units, AMD-V Nested Paging virtualization, and HyperTransport 3.0 are introduced in the Family 10h microarchitecture. Barcelona was the first design which implemented it.
  • AMD Turion X2 Ultra Family 11h microarchitecture - The Family 11h microarchitecture is a mixture of elements of both K8 and K10 to address the requirements for lower power consumption of the notebook market. It was marketed as the Turion X2 Ultra. It was later superseded by entirely K10-based notebook CPU designs.
  • Llano Family 12h microarchitecture - The Family 12h microarchitecture is an evolution of the K10 design featuring a 1 MB L2 cache per core, no L3 cache, improvements to the hardware prefetcher, a redesigned memory controller, power-saving improvements including clock gating, and Onion and Garlic interfaces for interfacing with an on-die GPU. It was used in first generation AMD Fusion A10[citation needed], A8, A6, A4 and E2 CPUs.
  • AMD Bobcat Family 14h microarchitecture - The Family 14h microarchitecture, codenamed Bobcat, is a new distinct line from the original AMD64 microarchitectures, which is aimed in the 1 W to 10 W power category; the microprocessor core is in fact a very simplified x86 core. Ontario and Zacate were the first designs which implemented it.
  • AMD Bulldozer Family 15h microarchitecture - The Family 15h microarchitecture, codenamed Bulldozer, is the latest successor of the Family 10h microarchitecture by way of Fusion Family 12h. Bulldozer is designed for processors in the 10 W to 220 W category, implementing XOP, FMA4 and CVT16 instruction sets.[1] Orochi was the first design which implemented it.
  • Family 16h microarchitecture Jaguar - Successor to Bobcat. Kabini and Temash. Puma - Successor to Jaguar. Beema and Mullins.

Comparison of AMD x86 Microarchitecture[edit]

Other microarchitectures[edit]

See also[edit]

References[edit]

External links[edit]