List of MIPS microarchitectures

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This is a sub-article to MIPS instruction set.

These are listings of microarchitectures based on the MIPS family of instruction sets, sorted by year, process size, frequency, die area, and so on. The microarchitectures are designed by MIPS Technologies/Imagination Technologies and third parties. It is displaying an overview of the MIPS processor lineup with performance and functionality versus capabilities for the more recent MIPS Aptiv device families.

Linux kernel version 3.14 incorporated support for the interAptiv and proAptiv processor cores.[1]

MIPS microprocessor cores[edit]

Designed by MIPS Technologies[edit]

MIPS Microprocessors
MIPS instruction set Microarchitecture Year Process (nm) Frequency (MHz) Transistors (millions) Die Area (mm2) Pin Count Power (W) Voltage (V) D. cache (kB) I. cache (kB) MMU L2 Cache L3 Cache Features
MIPS I R2000 1985 2000 8 to 16.67 0.11 80 64 external 64 external none none 5 stage pipelines, FPU: 2010; Sony PlayStation
R3000 1988 1200 20 to 40 0,11 40 145 4 32 32 1 MB external none same as R2000; FPU: 3010
MIPS II R6000 1990 60 to 66 external external none none 32-bit register size, 36-bit physical address, FPU; A 32 bit ECL microprocessor manufactured by a company called Bipolar Integrated Technology (BIT). Production problems with the chip almost killed MIPS Computers and led to it being taken over by SGI. The CMOS R4000 followed hot on the R6000's heels and was cheaper, cooler, and higher performance as well as being 64 bit so the 6000 quickly become a minor footnote in RISC computing history.
MIPS III R4000 1991 800 100 1.35 213 179 15 5 8 8 none
R4400 1992 600 100 to 250 2.3 186 179 15 5 8 8 none
R4200 1993 600 80 1.3 81 179 1.8-2.0 3.3 8 16 128kB to 4MB external none scalar design with a five-stage classic RISC pipeline
R4300i 1995 350 100 / 133 45 120 2.2 3.3 none
R4600 1994 640 100 / 133 2.2 77 179 4.6 5 16 16 512 kB external none
R4650 1994 640 133 / 180 2.2 77 179 4.6 5 16 16 512 kB external none
R4640 1995 640 179 none
R4700 1996 500 100 to 200 2.2 179 16 16 External none
MIPS IV R5000 1996 350 150 to 200 3.7 84 223 10 3.3 32 32 1 MB external none
RM7000 1998 250, 180, 130 250 to 600 18 91 304 10, 6, 3 3.3, 2.5, 1.5 16 16 256kB internal 1MB external
R8000 1994 700 75 to 90 2.6 299 591 30 3.3 16 16 4 MB External none superscalar, up to 4 ins. Per cycle
R10000 1996 350, 250 150 to 250 6.7 350 599 30 3.3 32 32 512 kB – 16 MB external none
R12000 1998 350, 250 270 to 360 7.15 229 600 20 4 32 32 512 kB – 16 MB external none single-chip 4-issue superscalar
R12000A 2000 180 400 none
R14000 2001 130 500 7.2 204 527 17 32 32 512 kB – 16 MB external none
R14000A 2002 130 600 17 32 32 none
R16000 2003 110 700 to 1000 20 64 64 512 kB – 16 MB external none
R16000A 2004 110 800 to 1000 64 64 none
R18000 2001 130 1.2 1 MB none was planned, but not manufactured
MIPS V H1 "Beast" none was planned, but not manufactured
H2 "Captain" none was planned, but not manufactured
MIPS32 4K 1999 none
4KE none
24K 2003 130,65,40 400 (130 nm) 750 (65 nm) 1468 (40 nm) 0.83 64 64 4–16 MB external none
24KE 2003 130,65,40 none The MIPS32 24KE Core Family: High-Performance RISC Cores with DSP Enhancements
34K 2006 90, 65, 40 500 (90 nm) 1454 (40 nm) none
74K 2007 65 1080 none
1004K 2008 65 1100 none
1074K 2010 40 1500 none
1074Kf 2010 40 none Floating point
microAptiv 2012 90, 65 8 to 64 8 to 64 none
interAptiv 2012 4 to 64 4 to 64 up to 8MB internal none
proAptiv 2012 32 or 64 32 or 64 up to 8MB internal none
MIPS64 5K 1999
20K 2000

Designed by Imagination Technologies[edit]

MIPS Technologies was acquired December, 17th 2012 by Imagination Technologies. Since then, the following products hit the market.

The Warrior P-Class CPU was announced on 14 October 2013[2]

The CPU IP cores comprising the MIPS Series5 ‘Warrior’ family are based on MIPS32 release 5 and will come in three classes of performance and features:

  • ‘Warrior M-class’: entry-level MIPS cores for embedded and microcontroller applications, a progression from the popular microAptiv family
  • ‘Warrior I-class’: mid-range, feature-rich MIPS CPUs following on from the highly efficient interAptiv family
  • ‘Warrior P-class’: high-performance MIPS processors building on the award-winning proAptiv family

Since Imagination Technologies is a founding member of the HSA Foundation[3] it remains to be seen which features described by Heterogeneous System Architecture will be present in the products.

Designed by third parties[edit]

A couple of companies purchased a license for the MIPS instruction set. Based upon it, they develop own CPU microarchitectures.

MIPS instruction set Licensee Microarchitecture Features Year Process (nm) Frequency (MHz) Transistors (millions) Die Size (mm2) Pin Count Power (W) Voltage (V) D. cache (kB) I. cache (kB) MMU L2 Cache L3 Cache
MIPSIII Sony Computer Entertainment + Toshiba Emotion Engine
MIPS32 Alchemy Semiconductor Au1
Broadcom BMIPS3000
BMIPS4000
BMIPS5000
BCM53001 65 400 32 32
BCM1255
Ingenic Semiconductor XBurst 1 single issue, 8-stage pipeline 2005 180, 130, 64, 40 240 0.15 1.8 16 16 yes none none
MIPS64 SiByte SB1
Broadcom BCM1125H 400-800 4w @ 400 MHz 32 32 yes 256KB
BCM1255 Dualcore, DDR2, 4x Gigabit LAN 800-1200 13W @ 1 GHz 32 32 yes 512KB
Cavium Octeon: CN30xx, CN31xx, CN36xx, CN38xx 2006
Octeon Plus: CN5xxx 2007
Octeon II: CN6xxx 2009
Octeon III: CN7xxx 2012
Ingenic Semiconductor XBurst 2 dual-issue/dual-threaded 2013 40 240 0.15 1.8 16 16 yes none none
NEC VR4305
VR4310
NXP Semiconductors  ??
 ??
CAS: ICT none yet
 ??

Other[edit]

  • PhysX P1 was a multi-core PPU using the MIPS instruction set.

See also[edit]

References[edit]