Low Pin Count

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Low Pin Count interface IT8705F Super I/O chip. Data sheet available from ITE Tech. Inc.[1]
Trusted Platform Module installed on a motherboard, and using the LPC bus

The Low Pin Count bus, or LPC bus, is used on IBM-compatible personal computers to connect low-bandwidth devices to the CPU, such as the boot ROM, "legacy" I/O devices (integrated into a super I/O chip), and Trusted Platform Module (TPM).[2] "Legacy" I/O devices usually include serial and parallel ports, PS/2 keyboard, PS/2 mouse, and floppy disk controller.

The physical wires of the LPC bus usually connect to the southbridge chip on a PC motherboard, which contains the circuit equivalents of the "legacy" onboard peripherals of the IBM PC/AT architecture, such as the two programmable interrupt controllers, the programmable interval timer, and two ISA DMA controllers.


The LPC bus was introduced by Intel in 1998 as a substitute for the Industry Standard Architecture (ISA) bus. It resembles ISA to software, although physically it is quite different. The ISA bus has a 16-bit wide data bus and a 24-bit address bus that can be used for both 16-bit I/O port addresses and 24-bit memory addresses; both run at speeds up to 8.33 MHz. The LPC bus uses a 4-bit-wide bus operating at four times the clock speed (33.3 MHz) for 16-bit I/O port addresses, 32-bit memory addresses, and for data.

LPC's main advantage is that it requires only seven signals, and is therefore easy to route on modern motherboards, which are often quite crowded. An integrated circuit using LPC will need 30 to 72 fewer pins than its ISA equivalent. The clock rate was chosen to match that of PCI in order to further ease integration. Also, LPC is intended to be a motherboard-only bus. No connector is defined, and no LPC peripheral daughterboards are available, except motherboard-specific Trusted Platform Modules (TPMs).[2] Device discovery is not supported; since only motherboard devices or specific models of TPM are connected, the host firmware (BIOS, UEFI) image will include a static description of any devices and their I/O addresses expected to be present on a particular motherboard.

The LPC specification defines seven mandatory signals required for bidirectional data transfer. Four of these signals carry the multiplexed address and data. The other three—​frame, reset, and clock—​are control signals, the latter two of which can be shared with the PCIRST# and PCICLK signals.

Six optional signals defined in the specification can be used for interrupt support, direct memory access, waking the system from a low power ("sleeping") state and notifying the LPC peripherals that power will soon be removed.

LPC data transfer rates depend on the type of bus access (I/O, Memory, DMA, firmware) performed and by the speed of the host and the LPC device. Overhead dominates all bus cycles except the 128-byte firmware read cycle, in which 256 of the 273 clock ticks consumed by this cycle actually are used to transfer data to get a throughput of 15.63 MB/s.[3] The next fastest bus cycle, the 32-bit ISA-style DMA write cycle that was defined in this standard, can transfer up to 6.67 MB/s because only 8 out of 20 clock ticks used in this bus cycle actually transfer data with the rest of the cycles are overhead.[3]

A CPLD or FPGA can implement a LPC host or a LPC peripheral.[4]

The original Xbox game console has an LPC debug port that can be used to force the Xbox to boot new code.[5][6]

Intel designed the LPC bus so that the System BIOS could be stored in a single flash memory chip directly connected to the LPC bus. Intel also made it possible to put operating system images and software applications on a single flash memory chip directly connected to the LPC bus, as an alternative to a Parallel ATA port.[7]

Supported peripherals[edit]

The LPC bus specification limits what type of peripherals may be connected to it. It only allows devices that belong to the following classes of devices: super I/O devices, integrated audio including either AC'97 devices or devices that implemented the Sound Blaster interface, and generic-application memory including nonvolatile BIOS memory, firmware hubs, and embedded controllers. Furthermore, each class is restricted on which bus cycles are allowed for each class.[3]

Super I/O devices and audio devices are allowed to accept I/O cycles, accept ISA-style third-party DMA cycles, and generate bus master cycles. Generic-application memory devices like nonvolatile BIOS memory and LPC flash devices are allowed to accept memory cycles. Firmware hubs are allowed to accept firmware memory cycles. Embedded controllers are allowed to accept I/O cycles and generate bus master cycles. Some ISA cycles that were deemed not useful to these classes were removed. They include host-initiated two-byte memory cycles and host-initiated two-byte I/O cycles. These removed transfer types could be initiated by the host on ISA buses but not on LPC buses. The host would have to simulate two-byte cycles by splitting them up into two one-byte cycles. The ISA bus has a similar concept because the original 8-bit ISA bus required 16-bit cycles to be split up. Therefore, the 16-bit ISA bus automatically split 16-bit cycles into 8-bit cycles for the benefit of 8-bit ISA peripherals unless the ISA device being targeted by a 16-bit memory or I/O cycle asserted a signal that told the bus that it could accept the requested 16-bit transfer without assistance from an ISA cycle splitter.[8] ISA-style bus mastering has been replaced in the LPC bus with a bus mastering protocol that does not rely on the ISA-style DMA controllers at all. This was done in order to remove ISA's limit on the number of peripherals that could perform bus mastering. Both ISA-style third-party DMA and ISA-style bus mastering require the peripheral to monopolize one of the DMA channels, which could get scarce in a bus with many peripherals that use DMA channels. The ISA-style bus cycles that were inherited by LPC from ISA are one-byte host-initiated I/O bus cycles, one-byte host-initiated memory cycles, and one- or two-byte host-initiated ISA-style DMA cycles.[3]

However, some non-ISA bus cycles were added. Cycles that were added to improve the performance of devices beside firmware hubs include LPC-style one-, two-, and four-byte bus master memory cycles; one-, two-, and four-byte bus master I/O cycles; and 32-bit third-party DMA which conforms to all of the restrictions of ISA-style third-party DMA except for the fact that it can do 32-bit transfers. Any device that is allowed to accept traditional ISA-style DMA is also allowed to use this 32-bit ISA-style DMA. The host could initiate 32-bit ISA-style DMA cycles, while peripherals could initiate bus master cycles. Firmware hubs consumed firmware cycles that were designed just for firmware hubs so that firmware addresses and normal memory-mapped I/O addresses could overlap without conflict. Firmware memory reads could read one, two, four or 128 bytes at once. Firmware memory writes could write one, two or four bytes at once.[3]

See also[edit]


  1. ^ "IT8705F EC-LPC I/O product information". ite.com.tw. Archived from the original on 2012-02-19. Retrieved 2014-04-27. 
  2. ^ a b Johannes Winter (2011). "A Hijacker's Guide to the LPC bus". tugraz.at. Retrieved 2013-12-19. 
  3. ^ a b c d e Intel LPC Interface Specification 1.1
  4. ^ "LPC Bus Controller". Lattice Reference Design RD1049. 2011.
  5. ^ Andrew Huang. "Hacking the Xbox: An Introduction to Reverse Engineering". 2003. p. 48 and p. 151.
  6. ^ O. Theis. "Modding the XBox". section "Details of the LPC".
  7. ^ Sharon Dagan. "Flash Storage Alternatives for the Low-Pin-Count (LPC) Bus". EE Times. 2002.
  8. ^ http://faculty.chemeketa.edu/csekafet/elt256/pcarch-full_isa-bus.pdf

External links[edit]