Low Pin Count
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The Low Pin Count bus, or LPC bus, is used on IBM-compatible personal computers to connect low-bandwidth devices to the CPU, such as the boot ROM and the "legacy" I/O devices (behind a super I/O chip). The "legacy" I/O devices usually include serial and parallel ports, PS/2 keyboard, PS/2 mouse, floppy disk controller and — more recently — the Trusted Platform Module (TPM). The physical wires of the LPC bus usually connect to the southbridge chip on a PC motherboard, which contains the circuit equivalents of the "legacy" onboard peripherals of the IBM PC/AT architecture, such as the two programmable interrupt controllers, the programmable interval timer, and the two ISA DMA controllers.
The LPC bus was introduced by Intel in 1998 as a substitute for the Industry Standard Architecture (ISA) bus. It resembles ISA to software, although physically it is quite different, replacing the 16-bit-wide, 8.33 MHz ISA bus with a 4-bit-wide bus operating at 4 times the clock speed (33.3 MHz).
LPC's main advantage is that it requires only seven signals, and is therefore easy to route on modern motherboards, which are often quite crowded. An integrated circuit using LPC will need 30 to 72 fewer pins than its ISA equivalent. The clock rate was chosen to match that of PCI in order to further ease integration. Also, LPC is intended to be a motherboard-only bus. No connector is defined, and no LPC peripheral daughterboards are available, except motherboard-specific Trusted Platform Modules (TPMs). There is no configuration in terms of device discovery. Since only motherboard devices are connected, or specific TPMs, the host firmware (BIOS, UEFI) "knows" how to set them up and deal with them.
The LPC specification defines seven mandatory signals required for bidirectional data transfer. Four of these signals carry the multiplexed address and data. The other three — frame, reset, and clock — are control signals, the latter two of which can be shared with the PCIRST# and PCICLK signals.
Six optional signals defined in the specification can be used for interrupt support, direct memory access, waking the system from a low power ("sleeping") state and notifying the LPC peripherals that power will soon be removed.
A CPLD or FPGA can implement a LPC host or a LPC peripheral.
Intel designed the LPC bus so that the System BIOS could be stored in a single flash memory chip directly connected to the LPC bus. Intel also made it possible to put operating system images and software applications on a single flash memory chip directly connected to the LPC bus, as an alternative to a Parallel ATA port.
- Johannes Winter (2011). "A Hijacker's Guide to the LPC bus". tugraz.at. Retrieved 2013-12-19.
- Intel LPC Interface Specification 1.1 - 32 bit DMA write (device to host)
- "LPC Bus Controller". Lattice Reference Design RD1049. 2011.
- Andrew Huang. "Hacking the Xbox: An Introduction to Reverse Engineering". 2003. p. 48 and p. 151.
- O. Theis. "Modding the XBox". section "Details of the LPC".
- Sharon Dagan. "Flash Storage Alternatives for the Low-Pin-Count (LPC) Bus". EE Times. 2002.
- Serialized IRQ Support For PCI Systems (Microsoft Word format)—used by the LPC bus
- Open-Source LPC Host and Peripheral Cores