|Original author(s)||Stuart Feldman|
|Type||Software development tools|
Makefile(s) are text files written in a certain prescribed syntax. Together with Make Utility, it helps build a software from its source files, a way to organize code, and its compilation and linking.
Most often, the Makefile tells make how to compile and link a program. Using C/C++ as an example, when a C/C++ source file is changed, it must be recompiled. If a header file has changed, each C/C++ source file that includes the header file must be recompiled to be safe. Each compilation produces an object file corresponding to the source file. Finally, if any source file has been recompiled, all the object files, whether newly made or saved from previous compilations, must be linked together to produce the new executable program. These instructions with their dependencies are specified in a Makefile.
Makefiles originated in Unix like systems and is still the primary software build mechanism.
Windows supports a variation of makefiles with its nmake utility. Standard Unix like makefiles can be executed in Windows in a Cygwin environment.
However, Visual Studio is a very popular software development environment in Windows which does not use makefiles. The equivalent of a Makefile is managed by Visual Studio Project and Solution files.
Makefiles contain five kinds of things: explicit rules, implicit rules, variable definitions, directives, and comments.
- An explicit rule says when and how to remake one or more files, called the rule's targets. It lists the other files that the targets depend on, called the prerequisites of the target, and may also give a recipe to use to create or update the targets.
- An implicit rule says when and how to remake a class of files based on their names. It describes how a target may depend on a file with a name similar to the target and gives a recipe to create or update such a target.
- A variable definition is a line that specifies a text string value for a variable that can be substituted into the text later.
- A directive is an instruction for make to do something special while reading the makefile such as reading another makefile.
- ‘#’ in a line of a makefile starts a comment. It and the rest of the line are ignored.
A makefile consists of “rules” with the following construct.
target: dependencies [tab] system command(s)
Note: It is important to insert a [tab] character before the commands.
A target is usually the name of a file that is generated by a program; examples of targets are executable or object files. A target can also be the name of an action to carry out, such as 'clean'.
A dependency (also called prerequisite) is a file that is used as input to create the target. A target often depends on several files. However, the rule that specifies a recipe for the target need not have any prerequisites. For example, the rule containing the delete command associated with the target 'clean' does not have prerequisites.
The system command(s) (also called recipe) is an action that make carries out. A recipe may have more than one command, either on the same line or each on its own line.
A Makefile is executed with the make command.
make [options] [target1 target2 ...]
By default, when make looks for the makefile, it tries the following names, in order: makefile and Makefile.
Here is a simple makefile that describes the way an executable file called edit depends on four object files which, in turn, depend on four C source and two header files.
edit : main.o kbd.o command.o display.o cc -o edit main.o kbd.o command.o display.o main.o : main.c defs.h cc -c main.c kbd.o : kbd.c defs.h command.h cc -c kbd.c command.o : command.c defs.h command.h cc -c command.c display.o : display.c defs.h cc -c display.c clean : rm edit main.o kbd.o command.o display.o
To use this makefile to create the executable file called edit, type: make
To use this makefile to delete the executable file and all the object files from the directory, type: make clean