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In the design of modern personal computers, memory geometry describes the internal structure of random-access memory. Memory geometry is of concern to consumers upgrading their computers, since older memory controllers may not be compatible with later products. Memory geometry terminology can be confusing because of the number of overlapping terms.
Memory geometry describes the logical configuration of a RAM module, but consumers will always find it easiest to grasp the physical configuration. Much of the confusion surrounding memory geometry occurs when the physical configuration obfuscates the logical configuration. The first defining feature of RAM is form factor. RAM modules can be in compact SO-DIMM form for space constrained applications like laptops, printers, embedded computers, and small form factor computers, and in DIMM format, which is used in most desktops.
The other physical characteristics, determined by physical examination, are the number of memory chips, and whether both sides of the memory "stick" are populated. Modules with the number of chips equal to some power of 2 do not support memory error detection or correction. If there are extra chips (between powers of 2), these are used for ECC. RAM modules are 'keyed' by indentations on the sides, and along the bottom of the module. This determines the technology, and classification of the modules, for instance whether it is DDR2, or DDR3, and whether it is suitable for desktops, or for servers. It is important to make sure that the keying of the module matches the key of the slot it is intended to occupy. Additional, non-memory chips on the module are an indication that it could be designed for high capacity memory systems for servers, and that the module may be incompatible with desktop systems.
As the next section of this article will cover the logical architecture, which covers the logical structure spanning every populated slot in a system, the physical features of the slots themselves becomes important. By consulting the documentation of your motherboard, or reading the labels on the board itself, you can determine the underlying logical structure of the slots. When there is more than one slot, they are numbered, and when there is more than one channel, the different slots are separated in that way as well - usually color-coded.
In the 90s specialized computers were released where two computers that each had their own memory controller could be networked at such a low level that the software run could use the memory, or CPU of either computer as if they were one unit. With AMD's release of the Opteron, and Intel's corresponding systems that share more than one memory controller in a single system have become common in applications that require the power of more than one common desktop. For these systems schemes like Non-Uniform Memory Architecture are used.
Channels are the highest level structure at the local memory controller level. Modern computers can have two, three or even more channels. It is usually important that, for each module in any one channel, there is a logically identical module in the same location on each of the other populated channels.
Module capacity is the aggregate space in a module measured in byte, or - more generally - in words. Module capacity is equal to the product of the rank density and the number of ranks, and where the rank density is the product of rank depth, and rank width. The standard format for expressing this specification is (rank density) Mbit x (rank width)x(number of ranks).
Ranks are sub-units of a memory module which share the same address and data buses and are selected via CS (Chip Select) in low level addressing. For example, take a memory module with 8 chips on each side, with each chip having 8 bit wide data bus, then that module would have one rank for each side for a total of 2 ranks, if we define a rank to be 64 bits wide. Another example: Take a module composed of Micron Technology MT47H128M16 chips with the organization 128Mb x 16, meaning 128Meg memory depth and 16 bit wide data bus per chip. If the module has 8 of these chips on each side of the board, there would be a total of 16 chips x 16 bit wide data = 256 total bits wide of data. For a 64-bit wide memory data interface, this equates to having 4 ranks, where each rank can be selected via a 2-bit Chip Select signal. Memory controllers such as the Intel 945 Chipset list the configurations they support: "Supports 256-Mb, 512-Mb, and 1-Gb DDR2 technologies for x8 and x16 devices." "Supports four ranks for all DDR2 devices up to 512-Mbit density. Supports eight ranks for 1-Gbit DDR2 devices." As an example, take an i945 memory controller with 4 Kingston KHX6400D2/1Gs memory modules, where each module has a capacity of 1GiB. Kingston describes each module as composed of 16 chips with each chip having 8-bit wide data bus. Therefore, each module has 4 ranks. So from the MCH point of view there are 4 1GB modules. At a higher logical level, the MCH also sees 2 channels, each with 8 ranks.
In contrast, banks, while similar from a logical perspective to ranks, are implemented quite differently in physical hardware. Banks are sub-units inside a single memory chip, while ranks are sub-units composed of a subset of the chips on a module. Similar to Chip Select, banks are selected via Bank Select bits which are part of the memory interface.
Hierarchy of organization
The lowest form of organization covered by memory geometry, sometimes called "memory device". These are the component ICs that make up each module, or module of RAM. The most important measurement of a chip is its density, measured in bits. Because memory bus width is usually larger than the number of chips, most chips are designed to have width, meaning that they are divided into equal parts internally, and when one address "depth" is called up, instead of returning just one value, more than one value is returned. In addition to the depth, a second addressing dimension has been added at the chip level, banks. Banks allow one bank to be available, while another bank is unavailable because it is refreshing.
Some measurements of modules are size, width, speed, and latency. A memory module consists of a multiple of the memory chips to equal the desired module width. So a 32-bit SIMM module could be composed of four 8-bit wide (x8) chips. As noted in the memory channel part, one physical module can be made up of one or more logical ranks. If that 32-bit SIMM were composed of eight 8-bit chips the SIMM would have two ranks.
A memory channel is made up of ranks. Physically a memory channel with just one memory module might present itself as having one or more logical ranks.
This is the highest level. In a typical computer there will only be a single memory controller with only one or two channels. The logical features section described NUMA configurations, which can take the form of a network of memory controllers. For example, each socket of a two socket AMD K8 can have a two channel memory controller, giving the system a total of four memory channels.
Memory Geometry Notation
Various methods of specifying memory geometry can be encountered, giving different types of information.
(Memory Depth) x (Memory Width)
The Memory Width specifies the data width of the memory module interface in bits. For example, 64 would indicate a 64-bit data width, as is found on non-ECC DRAM modules of family SDR and DDR1-3. A memory of width of 72 would indicate an ECC module, with 8 extra bits in the data width for parity. The Memory Depth is the total memory capacity in bits divided by the non-parity memory width. Sometimes the memory depth is indicated in units of Meg (220), as in 32x64 or 64x64, indicating 32Meg depth and 64Meg depth, respectively.
This is the total memory capacity of the chip. Example: 128Mb.
(Memory Depth) x (Memory Width)
Memory Depth is the Memory Density divided by Memory Width. Example: For a memory chip with 128Mb capacity and 8 bit wide data bus, it can be specified as: 16Meg x 8. Sometimes the "Meg" is dropped, as in 16x8.
(Memory Depth per bank) x (Memory Width) x (Number of Banks)
Example: A chip with the same capacity and memory width as above but constructed with 4 banks would be specified as: 4Meg x 8 x 4.
- List of device bandwidths
- Dynamic random access memory
- Random-access memory
- Memory organisation
- Memory address
- Memory bank
- Bank switching
- Double-sided RAM
- Dual-channel architecture
- Page address register
- kingston.com - Ultimate Memory Guide, 2007 (via archive.org)