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Column Address Strobe (CAS) latency, or CL, is the delay time between the moment a memory controller tells the memory module to access a particular memory column on a RAM module, and the moment the data from the given array location is available on the module's output pins. In general, the lower the CAS latency, the better.
In asynchronous DRAM, the interval is specified in nanoseconds. In synchronous DRAM, the interval is specified in clock cycles. Because the latency is dependent upon a number of clock ticks instead of an arbitrary time, the actual time for an SDRAM module to respond to a CAS event might vary between uses of the same module if the clock rate differs.
RAM operation background
Dynamic RAM is arranged in a rectangular array. Each row is selected by a horizontal word line. Sending a logical high signal along a given row enables the MOSFETs present in that row, connecting each storage capacitor to its corresponding vertical bit line. Each bit line is connected to a sense amplifier that amplifies the small voltage change produced by the storage capacitor. This amplified signal is then output from the DRAM chip as well as driven back up the bit line to refresh the row.
When no word line is active, the array is idle and the bit lines are held in a precharged state, with a voltage halfway between high and low. This indeterminate signal is deflected towards high or low by the storage capacitor when a row is made active.
To access memory, a row must first be selected and loaded into the sense amplifiers. This row is then active, and columns may be accessed for read or write.
The CAS latency is the delay between the time at which the column address and the column address strobe signal are presented to the memory module and the time at which the corresponding data is made available by the memory module. The desired row must already be active; if it is not, additional time is required.
As an example, a typical 1 GiB SDRAM memory module might contain eight separate one-gibibit DRAM chips, each offering 128 MiB of storage space. Each chip is divided internally into eight banks of 227=128 Mibits, each of which composes a separate DRAM array. Each array contains 214=16384 rows of 213=8192 bits each. One byte of memory (from each chip; 64 bits total from the whole DIMM) is accessed by supplying a 3-bit bank number, a 14-bit row address, and a 10-bit column address.
Effect on memory access speed
With asynchronous DRAM, the time delay between presenting a column address and receiving the data on the output pins is constant. Synchronous DRAM, however, has a CAS latency that is dependent upon the clock rate. Accordingly, the CAS latency of an SDRAM memory module is specified in clock ticks instead of real time.
Because memory modules have multiple internal banks, and data can be output from one during access latency for another, the output pins can be kept 100% busy regardless of the CAS latency through pipelining; the maximum attainable bandwidth is determined solely by the clock speed. Unfortunately, this maximum bandwidth can only be attained if the address of the data to be read is known long enough in advance; if the address of the data being accessed is not predictable, pipeline stalls can occur, resulting in a loss of bandwidth. For a completely unknown memory access (AKA Random access), the relevant latency is the time to close any open row, plus the time to open the desired row, followed by the CAS latency to read data from it. Due to spatial locality, however, it is common to access several words in the same row. In this case, the CAS latency alone determines the elapsed time.
In general, the lower the CAS latency, the better. Because modern DRAM modules' CAS latencies are specified in clock ticks instead of time, when comparing latencies at different clock speeds, latencies must be translated into actual times to make a fair comparison; a higher numerical CAS latency may still be a shorter real-time latency if the clock is faster. However, it is important to note that the manufacturer-specified CAS latency typically assumes the specified clock rate, so underclocking a memory module may also allow for a lower CAS latency to be set.
Double data rate RAM operates using two transfers per clock cycle. The transfer rate is typically quoted by manufacturers, instead of the clock rate, which is half of the transfer rate for DDR modules. Because the CAS latency is specified in clock cycles, and not transfer ticks (which occur on both the positive and negative edge of the clock), it is important to ensure it is the clock rate that is being used to compute CAS latency times, and not the doubled transfer rate.
Another complicating factor is the use of burst transfers. A modern microprocessor might have a cache line size of 64 bytes, requiring eight transfers from a 64-bit-wide (8 bytes) memory to fill. The CAS latency can only accurately measure the time to transfer the first word of memory; the time to transfer all eight words depends on the data transfer rate as well. Fortunately, the processor typically does not need to wait for all eight words; the burst is usually sent in critical word first order, and the first critical word can be used by the microprocessor immediately.
In the table below, data rates are given in million transfers—also known as Megatransfers—per second (MT/s), while clock rates are given in MHz, million cycles per second.
Memory timing examples
|Generation||Type||Data rate||Bit time||Command rate||Cycle time||CAS latency||First word||Fourth word||Eighth word|
|SDRAM||PC100||100 MT/s||10 ns||100 MHz||10 ns||2||20 ns||50 ns||90 ns|
|PC133||133 MT/s||7.5 ns||133 MHz||7.5 ns||3||22.5 ns||45 ns||75 ns|
|DDR SDRAM||DDR-333||333 MT/s||3 ns||166 MHz||6 ns||2.5||15 ns||24 ns||36 ns|
|DDR-400||400 MT/s||2.5 ns||200 MHz||5 ns||3||15 ns||22.5 ns||32.5 ns|
|2.5||12.5 ns||20 ns||30 ns|
|2||10 ns||17.5 ns||27.5 ns|
|DDR2 SDRAM||DDR2-667||667 MT/s||1.5 ns||333 MHz||3 ns||5||15 ns||19.5 ns||25.5 ns|
|4||12 ns||16.5 ns||22.5 ns|
|DDR2-800||800 MT/s||1.25 ns||400 MHz||2.5 ns||6||15 ns||18.75 ns||23.75 ns|
|5||12.5 ns||16.25 ns||21.25 ns|
|4.5||11.25 ns||15 ns||20 ns|
|4||10 ns||13.75 ns||18.75 ns|
|DDR2-1066||1066 MT/s||0.95 ns||533 MHz||1.9 ns||7||13.13 ns||15.94 ns||19.69 ns|
|6||11.25 ns||14.06 ns||17.81 ns|
|5||9.38 ns||12.19 ns||15.94 ns|
|4.5||8.44 ns||11.25 ns||15 ns|
|4||7.5 ns||10.31 ns||14.06 ns|
|DDR3 SDRAM||DDR3-1066||1066 MT/s||0.9375 ns||533 MHz||1.875 ns||7||13.13 ns||15.95 ns||19.7 ns|
|DDR3-1333||1333 MT/s||0.75 ns||666 MHz||1.5 ns||9||13.5 ns||15.75 ns||18.75 ns|
|6||9 ns||11.25 ns||14.25 ns|
|DDR3-1375||1375 MT/s||0.73 ns||687 MHz||1.5 ns||5||7.27 ns||9.45 ns||12.36 ns|
|DDR3-1600||1600 MT/s||0.625 ns||800 MHz||1.25 ns||11||13.75 ns||15.625 ns||18.125 ns|
|10||12.5 ns||14.375 ns||16.875 ns|
|9||11.25 ns||13.125 ns||15.625 ns|
|8||10 ns||11.875 ns||14.375 ns|
|7||8.75 ns||10.625 ns||13.125 ns|
|6||7.50 ns||9.375 ns||11.875 ns|
|DDR3-2133||2133 MT/s||0.469 ns||1066 MHz||0.938 ns||12||11.256 ns||12.663 ns||14.539 ns|
|11||10.318 ns||11.725 ns||13.601 ns|
|10||9.38 ns||10.787 ns||12.663 ns|
|9||8.442 ns||9.849 ns||11.725 ns|
|8||7.505 ns||8.911 ns||10.787 ns|
|DDR3-2400||2400 MT/s||0.417 ns||1200 MHz||0.833 ns||13||10.83 ns||12.08 ns||13.75 ns|
|12||10 ns||11.25 ns||13.75 ns|
|11||9.17 ns||10.42 ns||12.08 ns|
|10||8.33 ns||9.58 ns||11.25 ns|
|9||7.5 ns||8.75 ns||10.42 ns|
|Generation||Type||Data rate||Bit time||Command rate||Cycle time||CL||First word||Fourth word||Eighth word|
Formulas used to calculate latencies
- Command rate = Data rate/2
- Cycle time = 2*Bit time
- First word = ( (CAS latency*2) + (1-1) ) * Bit time
- Fourth worth = ( (CAS latency*2) + (4-1) ) * Bit time
- Eighth word = ( (CAS latency*2) + (8-1) ) * Bit time