Memory ordering

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Memory ordering is a group of properties of the modern microprocessors, characterizing their possibilities in memory operations reordering. It is a type of out-of-order execution. Memory reordering can be used to fully utilize different cache and memory banks.

On most modern uniprocessors memory operations are not executed in the order specified by the program code. But in single threaded programs from the programmer's point of view, all operations appear to have been executed in the order specified, with all inconsistencies hidden by hardware.

In symmetric multiprocessing (SMP) microprocessor systems[edit]

There are several memory-consistency models for SMP systems:

  • Sequential consistency (all reads and all writes are in-order)
  • Relaxed consistency (some types of reordering are allowed)
    • Loads can be reordered after loads (for better working of cache coherency, better scaling)
    • Loads can be reordered after stores
    • Stores can be reordered after stores
    • Stores can be reordered after loads
  • Weak consistency (reads and writes are arbitrarily reordered, limited only by explicit memory barriers)

On some CPUs

  • Atomic operations can be reordered with loads and stores.
  • There can be incoherent instruction cache pipeline, which prevents self-modifying code from being executed without special instruction cache flush/reload instructions.
  • Dependent loads can be reordered (this is unique for Alpha). If the processor fetches a pointer to some data after this reordering, it might not fetch the data itself but use stale data which it has already cached and not yet invalidated. Allowing this relaxation makes cache hardware simpler and faster but leads to the requirement of memory barriers for readers and writers.[1]
Memory ordering in some architectures[2][3]
Type Alpha ARMv7 PA-RISC POWER SPARC RMO SPARC PSO SPARC TSO x86 x86 oostore AMD64 IA-64 zSeries
Loads reordered after loads Y Y Y Y Y Y Y
Loads reordered after stores Y Y Y Y Y Y Y
Stores reordered after stores Y Y Y Y Y Y Y Y
Stores reordered after loads Y Y Y Y Y Y Y Y Y Y Y Y
Atomic reordered with loads Y Y Y Y Y
Atomic reordered with stores Y Y Y Y Y Y
Dependent loads reordered Y
Incoherent instruction cache pipeline Y Y Y Y Y Y Y Y Y Y

Some older x86 and AMD systems have weaker memory ordering[4]

SPARC memory ordering modes:

  • SPARC TSO = total store order (default)
  • SPARC RMO = relaxed-memory order (not supported on recent CPUs)
  • SPARC PSO = partial store order (not supported on recent CPUs)

Memory barrier types[edit]

See also: Memory barrier

Compiler memory barrier[edit]

These barriers prevent a compiler from reordering instructions, they do not prevent reordering by CPU.

  • The GNU inline assembler statement
asm volatile("" ::: "memory");

or even

__asm__ __volatile__ ("" ::: "memory");

forbids GCC compiler to reorder read and write commands around it.[5]




Hardware memory barrier[edit]

Many architectures with SMP support have special hardware instruction for flushing reads and writes.

lfence (asm), void_mm_lfence(void)
sfence (asm), void_mm_sfence(void)[9]
mfence (asm), void_mm_mfence(void)[10]
sync (asm)
sync (asm)
mf (asm)
dcs (asm)
dmb (asm)
dsb (asm)
isb (asm)

Compiler support for hardware memory barriers[edit]

Some compilers support builtins that emit hardware memory barrier instructions:

See also[edit]


  1. ^ Reordering on an Alpha processor by Kourosh Gharachorloo
  2. ^ Memory Ordering in Modern Microprocessors by Paul McKenney
  3. ^ Memory Barriers: a Hardware View for Software Hackers, Figure 5 on Page 16
  4. ^ Table 1. Summary of Memory Ordering, from "Memory Ordering in Modern Microprocessors, Part I"
  5. ^ GCC compiler-gcc.h
  6. ^ ECC compiler-intel.h
  7. ^ Intel(R) C++ Compiler Intrinsics Reference

    Creates a barrier across which the compiler will not schedule any data access instruction. The compiler may allocate local data in registers across a memory barrier, but not global data.

  8. ^ Visual C++ Language Reference _ReadWriteBarrier
  9. ^ SFENCE — Store Fence
  10. ^ MFENCE — Memory Fence
  11. ^ Data Memory Barrier, Data Synchronization Barrier, and Instruction Synchronization Barrier.
  12. ^ Atomic Builtins
  13. ^
  14. ^ MemoryBarrier macro
  15. ^ Handling Memory Ordering in Multithreaded Applications with Oracle Solaris Studio 12 Update 2: Part 2, Memory Barriers and Memory Fence [1]

Further reading[edit]