Memory rank

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A memory rank is a set of DRAM chips connected to the same chip select, and which are therefore accessed simultaneously. In practice they also share all of the other command and control signals, and only the data pins for each DRAM are separate (but the data pins are shared across ranks).

The term “rank” was created and defined by JEDEC, the memory industry standards group. On a DDR, DDR2, or DDR3 memory module, each rank has a 64-bit wide data bus (with an optional extra 8-bit chip ECC on some DIMMs). The number of physical DRAMs depends on their individual widths. For example, a rank of x8 (8-bit) DRAMs would consist of 8 physical chips (plus one for ECC), but a rank of x4 (4-bit) DRAMs would consist of 16 physical chips (plus two for ECC). Multiple ranks can coexist on a single DIMM, and modern DIMMs can consist of one rank (single rank), two ranks (dual rank), four ranks (quad rank), or eight ranks (octal rank).

There is little difference between a dual rank UDIMM and two single rank UDIMMs in the same memory channel, other than that the DRAMs reside on different PCBs. The electrical connections between the memory controller and the DRAMs are almost identical (with the possible exception of which chip selects go to which ranks). Increasing the number of ranks per DIMM is mainly intended to increase the memory density per channel. Too many ranks in the channel can cause excessive loading and decrease the speed of the channel. DRAM load on the CA (Command/Address) bus can be reduced by using registered memory.

From a performance point of view there are several aspects:

  • MultiRank Modules does allow to open 8 pages in each Rank (means 8 Wordlines (1 in each Bank) per DRAM are activated). This increases the possibility of getting a hit on an already open row address. This depends very much on the applications that are running and Memory controllers do have quite some intelligence to utilize this feature.
  • MultiRank Modules do have higher loading on the DQ (and on unbuffered DIMMs on CA) bus. Two ranks DDR3 systems still can run at DDR3-1600, but if there are more Ranks connected in one channel the speed will be reduced. It depends on the need for each individual application if it can utilize many open banks or is hit fast by a Bandwidth decrease.
  • With some limitations the Ranks can be accessed independently. The controller can e. g. send Write Data to one Rank, while it already starts a Read on another Rank. While the DRAM on one Rank takes the write data from the Databus the other already does some internal read related operations (e. g. activation of a row, internal transfer of the data to the outupt drivers). Once the bus is "free" from noise from the previous read the DRAM can drive out the data. Controlling all this interleaved accesses is to be done by the controller.
  • There is one very small performance reduction for multi rank systems as they require some pipeline stalls between accessing different Ranks. For two ranks on a single DIMM it might not even be required, but this parameter is often programmed independent of the Rank location in the System (if on the same DIMM or different DIMMs). Nevertheless this pipeline stall is negligible compared to the above mentioned effects.

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