Memory refresh

Memory refresh is the process of periodically reading information from an area of computer memory, and immediately rewriting the read information to the same area with no modifications. Each memory refresh cycle refreshes a succeeding area of memory. Memory refresh is most often associated with modern dynamic random access memory. Due to the problem of fading of charge in DRAM information stored in capacitors become 1's to 0's.To prevent this from happening,design engineers adds an extra circuitry to recharge cells periodically. This process is refresh. If a cell is less than half recharged,it is determined to be zero,and cell is not recharged.

However, several early computer memory technologies also required periodical processes similar in purpose. These technologies include delay line memory and Williams tube.

Compare with magnetic core memory where each memory cell needs to be refreshed after being read, but periodical refreshes are not necessary. Also, see static random access memory which is used in similar applications as dynamic random access memory, but does not require refreshing (hence labelled static as opposed to dynamic).

The two basic types of silicon memory (Static and Dynamic) both have advantages and dis-advantages. Static memory can be considered permanent while powered on, i.e. once written the memory stays until specifically changed and may be read with impunity with no detriment thus its use tends to be simple in terms of system design. The internal construction of each static memory cell however, is fairly complex thus on-chip density is relatively low and price-per-bit is high. The complexity of the static memory cell is also relatively slow to operate thus static memory tends to have lower bandwidths that equivalent dynamic storage. In dynamic memory the storage cell is formed by a "parasitic" capacitor that occurs naturally at the P-N junction of a single diode. This construction is minuscule and simple but over time the electrical charge on the cell (representing the stored data) fades so a high on-chip density with low-cost is mitigated by complexity in maintaining that charge with refresh circuitry. Writing the capacitor of the dynamic cell is very rapid and write-access times on modern dynamic storage can be in single digit nano-seconds.

Modern DRAM modules provide the refresh circuitry on-board with no requirement for motherboard circuitry, almost to the point where, at a module level, they may be thought of as static - requiring the CPU to do nothing to preserve their content. Some CPUs (e.g. the Zilog Z80) provided special internal registers that could provide the Row-Address Strobe (RAS) to refresh dynamic memory cells, the register being incremented on each refresh cycle. The availability of a RAS refresh was signalled by a unique combination of address and control wires during operationally redundant clock cycles (T-States), i.e. during instruction decode/execution when the buses may not be required. Instead of the bus being inactive during such t-states, the refresh register would be presented on the address bus along with a combination of control wires to indicate to the refresh circuitry. In early versions of the Z80 a lack of fore-sight resulted in the R register being only 7 bits long. With the rapid advent of 64Kbit+ DRAM chips (with an 8 bit RAS), extra circuitry had to be built around the refresh signal to synthesize the missing 8th bit and prevent blocks of memory being lost after a few milli-seconds. Usually in the form of an 8-bit counter chip, the output was used to provide the refresh RAS address instead of the R register. The refresh signal from the CPU was used as the clock for this counter resulting in the memory row to be refreshed being incremented with each refresh cycle. Later versions and licensed "work-alikes" of the Z80 core remedied the missing 8th bit and modern CPUs have greatly expanded on such basic provisioning to provide rich all-in-one solutions for DRAM refresh.