Mentec PDP-11

From Wikipedia, the free encyclopedia
Jump to: navigation, search

Mentec Limited was founded in 1978 and initially focused on the development of monitoring and control software and systems. It was a significant Digital reseller and OEM in Ireland. Mentec Computer Systems Limited was a subsidiary of Mentec Limited that developed PDP-11 processors. Mentec Inc.[1] was a US-based subsidiary of Mentec Limited. In the early 1980s it had a range of remote terminal units based on the SBC/11-21 (Falcon).

Once the J11 chip became available in 1982 Mentec commenced the design of its first PDP-11 single board computer the M70. In 1994 Digital transferred the PDP-11 operating systems to Mentec Inc.[2]

Product Range[edit]

M70[edit]

The M70 was developed between 1982 and 1984. It was a quad Q-bus module based on the J11 chipset incorporating on-board ECC DRAM, bootstrap eproms and 4 Serial lines implemented using DEC DC319 DLART chips.

M71[edit]

The M71 was a version of the M70 intended for process control.[3] It provided for 1/4 or 1 M Byte of ECC DRAM, up to 1/2 MB of EPROM, 4 serial lines (DC-319 DLARTs) and two parallel ports implemented using 8255 chips. It was initially designed by Mentec for use in its own Remote Terminal Units.

M80[edit]

The M80 was a further development of the M70 but using parity memory and a slightly higher clock rate.[4] It also introduced software configuration via the bootstrap which all but eliminated wire-wrap configuration.

M90[edit]

This was effectively merely a clock tweaked version of the M80.

M100[edit]

The M100 was the last of Mentec's J11 based processor boards.[5][6] It was a somewhat tidied up and faster re-design of the M90.

Some late models incorporated a daughter card with a Xilinx part which replaced the DLARTs and implemented a FIFO to prevent overruns for OEM applications.

A small number of late models incorporated an SRAM daughter card which replaced the on-board DRAM.

M11[edit]

The M11 was a microcoded re-implementation from scratch of the M100.[7] It was based around two Texas Instruments TI8832 ALUs and a TI 8818 microsequencer. One of the ALUs was used as the processor ALU while the second was used to implement the memory management unit. An Intel i960 processor was used to load the microcode, perform floating point (in IEEE format) and provide ODT. The 4 DLARTs of the earlier M100 were emulated on a single Xilinx part. All of the memory (both microcode and PDP-11 main memory) was implemented using SRAM. While not of any significant effect in the field it suffered from the fact that it used a large number of microcode controlled drivers onto tri-state buses, which made developing microcode somwehat hazardous.

The M11 design was implemented in VHDL and fully simulated using Mentor Graphics QuickSim II with behavioural language models for both the Q-Bus and console UART. It ran patched versions of the Digital PDP-11/23 CPU diagnostics on the simulator before any hardware was constructed.

M1[edit]

The M1 was an ASIC re-implementation of the M11. Despite being an ASIC implementation it was also fully microcoded.[8]

References[edit]