Message Signaled Interrupts
Message Signaled Interrupts (MSI) are an alternative in-band method of signaling an interrupt, using special in-band messages to replace traditional out-of-band assertion of dedicated interrupt lines. While more complex to implement in a device, message signaled interrupts have some significant advantages over pin-based out-of-band interrupt signaling.
Traditionally, a device has an interrupt line (pin) which it asserts when it wants to signal an interrupt to the host processing environment. This traditional form of interrupt signaling is an out-of-band form of control signaling since it uses a dedicated path to send such control information, separately from the main data path. Message signaled interrupts are replacing those dedicated interrupt lines with in-band signaling, where special messages indicating interrupts are exchanged through the main data path.
As an example, PCI Express does not have separate interrupt pins at all, and it uses special in-band messages to allow it to emulate an interrupt pin assertion or deassertion. Message signaled interrupts allow the device to write a small amount of data to a special memory-mapped I/O address; the chipset then delivers the corresponding interrupt to a processor.
A common misconception with Message Signaled Interrupts is that they allow the device to send data to a processor as part of the interrupt. The data that is sent as part of the write is used by the chipset to determine which interrupt to trigger on which processor; it is not available for the device to communicate additional information to the interrupt handler.
Some non-PCI architectures also use message signaled interrupts. For example, HP GSC devices do not have interrupt pins and can generate interrupts only by writing directly to the processor's interrupt register in memory space. The HyperTransport protocol also supports message signaled interrupts.
While more complex to implement in a device, message signaled interrupts have some significant advantages over pin-based out-of-band interrupt signaling. On the mechanical side, fewer pins makes for a simpler, cheaper, and more reliable connector. While this is no advantage to the standard PCI connector, PCI Express takes advantage of these savings.
MSI increases the number of interrupts that are possible. While conventional PCI was limited to four interrupts per card (and, because they were shared among all cards, most are using only one), message signaled interrupts allow dozens of interrupts per card, when that is useful.
There is also a slight performance advantage. In software, a pin-based interrupt could race with a posted write to memory. That is, the PCI device would write data to memory and then send an interrupt to indicate the DMA write was complete. However, a PCI bridge or memory controller might buffer the write in order to not interfere with some other memory use. The interrupt could arrive before the DMA write was complete, and the processor could read stale data from memory. To prevent this race, interrupt handlers were required to read from the device to ensure that the DMA write had finished. This read had a moderate performance penalty. An MSI write cannot pass a DMA write, so the race is eliminated.
PCI defines two optional extensions to support Message Signaled Interrupts, MSI and MSI-X. While PCI Express is compatible with legacy interrupts on the software level, it requires MSI or MSI-X.
MSI (first defined in PCI 2.2) permits a device to allocate 1, 2, 4, 8, 16 or 32 interrupts. The device is programmed with an address to write to (generally a control register in an interrupt controller), and a 16-bit data word to identify it. The interrupt number is added to the data word to identify the interrupt. Some platforms such as Windows do not use all 32 interrupts but only use up to 16 interrupts.
MSI-X (first defined in PCI 3.0) permits a device to allocate up to 2048 interrupts. The single address used by original MSI was found to be restrictive for some architectures. In particular, it made it difficult to target individual interrupts to different processors, which is helpful in some high-speed networking applications. MSI-X allows a larger number of interrupts and gives each one a separate target address and data word. Devices with MSI-X do not necessarily support 2048 interrupts but at least 64 which is double the maximum MSI interrupts.
Optional features in MSI (64-bit addressing and interrupt masking) are also mandatory with MSI-X.
On Intel systems, the LAPIC must be enabled for the PCI (and PCI Express) MSI/MSI-X to work, even on uniprocessor (single core) systems. In these systems, MSIs are handled by writing the interrupt vector directly into the LAPIC of the processor/core that needs to service the interrupt. The Intel LAPICs of 2009 supported up to 224 of MSI-based interrupts. According to a 2009 Intel benchmark using Linux, using MSI reduced the latency of interrupts by a factor of almost three when compared to I/O APIC delivery.
Some motherboard implementations, particularly among those with PCI to PCI-X bridges, have non-functional MSI support. The AMD-8131 and some ServerWorks PCI Express chipsets were among those with problems, at least under some versions of Linux. It has also been observed that some motherboards with Nvidia nForce chipsets have broken MSI support. As a result, when NVidia enabled the MSI support on their graphics card drivers for the first time, many users of the nForce-based motherboards complained of instability, what was eventually traced back to the MSI implementation of the motherboard.
Operating system support
In the Microsoft family of operating systems, Windows Vista and later versions have support for both MSI and MSI-X. Support was added in the Longhorn development cycle around 2004. MSI is not supported in earlier versions like Windows XP or Windows Server 2003.
- PCI Local Bus Specification Revision 2.2. Section 6.8 (MSI) (PCI-SIG). December 1998.
- PCI Local Bus Specification Revision 2.3. Section 6.8 (MSI) (PCI-SIG). 2002.
- PCI Local Bus Specification Revision 3.0. Section 6.8 (MSI & MSI-X) (PCI-SIG). August 2002.
- Don Anderson; Jay Trodden (2003). HyperTransport System Architecture. Addison-Wesley Professional. p. 200. ISBN 978-0-321-16845-0.
- Jonathan Corbet; Greg Kroah-Hartman; Alessandro Rubini (February 2005). "Linux Device Drivers, 3rd Edition". 15.4. Direct Memory Access. O'Reilly. Retrieved 2013-10-05.
- Microsoft. "Enabling Message-Signaled Interrupts in the Registry". Microsoft Corporation. Retrieved 12 April 2013.
- "Section 6.1: MSI & MSI-X". PCI Express Base Specification Revision 1.0a. PCI-SIG. April 2003.
- "Section 6.1: MSI & MSI-X". PCI Express Base Specification Revision 1.1. PCI-SIG. March 2005.
- "MSI-X Engineering Change Notice". "PCI Local Bus Specification Revision 2.3". PCI-SIG.
- APIC-Based Interrupt Subsystems on Uniprocessor PCs
- James Coleman, Reducing Interrupt Latency Through the Use of Message Signaled Interrupts, pp. 10-11
- James Coleman, Reducing Interrupt Latency Through the Use of Message Signaled Interrupts, p. 19
- Why can't I enable MSI on my motherboard?
- Interrupt Architecture Enhancements in Microsoft Windows Vista, Aug 11, 2004
- PCI, PCI-X, and PCI Express: Frequently Asked Questions, November 18, 2005, page 4
- John Stearns, Govinda Tatti, Edward Gillett and Anish Gupta, (March 27, 2006) Changes made to support MSI in Solaris Express Advanced Interrupt Handlers in the Solaris Express 6/05 OS
- John H. Baldwin, "PCI Interrupts for x86 Machines under FreeBSD", "availability" section
- MSI-HOWTO.txt first version
- With Myri10GE, can I use MSI-X interrupts on Linux 2.6.18 and earlier?