Message Signaled Interrupts
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Message Signaled Interrupts, in PCI 2.2 and later and PCI Express, are an alternative way of generating an interrupt. Traditionally, a device has an interrupt pin which it asserts when it wants to interrupt the host CPU. While PCI Express does not have separate interrupt pins, it has special messages to allow it to emulate a pin assertion or deassertion. Message Signaled Interrupts allow the device to write a small amount of data to a special address in memory space. The chipset will deliver the corresponding interrupt to a CPU.
There are several advantages to MSIs over pin-based interrupts. On the mechanical side, fewer pins reduce the cost of manufacture, the cost of design and the likelihood of mechanical failure. In software, a pin-based interrupt could race with a DMA write to memory. To prevent this race, interrupt handlers were required to read from the device to ensure that the DMA write had finished. This read had a moderate performance penalty. An MSI write cannot pass a DMA write, so no read from the device is necessary to fix this race.
PCI defines two different extensions to support Message Signaled Interrupts, MSI and MSI-X. MSI (defined in PCI 2.2) permits a device to allocate 1, 2, 4, 8, 16 or 32 interrupts. Each interrupt must go to the same address and the data written to that address are consecutive. This was quite restricitive for some architectures; for example it does not allow each interrupt to be separately targeted to individual processors on Intel x86 machines. In contrast, MSI-X (defined in PCI 3.0) allows a device to allocate any number of interrupts between 1 and 2048 and gives each interrupt separate data and address registers. Optional features in MSI (64-bit addressing and interrupt masking) are mandatory with MSI-X.
A common misconception with Message Signaled Interrupts is that they allow the device to send data to the CPU as part of the interrupt. The data that is sent as part of the write is used by the chipset to determine which interrupt to trigger on which CPU; it is not available for the device to communicate additional information to the interrupt handler.
Some non-PCI architectures also use Message Signaled Interrupts. For example, HP GSC devices do not have interrupt pins and can only interrupt by writing directly to the processor's interrupt register in memory space.
[edit] References
- The PCI 2.2 standard, section 6.8
- The MSI-X definition, freely available from the PCI SIG (also includes information on MSI)
[edit] External links
- MSDN paper on MSI in Windows Vista
- Linux MSI HOWTO
- Changes required to support MSI in FreeBSD (MSI / MSI-X Supported as of FreeBSD 6.3-RELEASE)
- Changes made to support MSI in Solaris Express
- Charlie Chen's Weblog: how does MSI-X work
