Mobile DDR

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This article is about computer memory. For the video game for Apple mobile phones, see Dance Dance Revolution S.

Mobile DDR (also known as mDDR, Low Power DDR, or LPDDR) is type of double data rate synchronous DRAM for mobile computers.

Bus width[edit]

In contrast with SDRAM, which is used in stationary devices and usually connected over a 64bit wide memory bus, LPDDR can be connected over 16bit or over 32bit memory bus per channel.[1]

Original LPDDR[edit]

The original low-power DDR (sometimes, in hindsight, called LPDDR1) is a slightly modified form of DDR SDRAM, with several changes to reduce overall power consumption.

Most significant, the supply voltage is reduced from 2.5 to 1.8 V. Additional savings come from temperature-compensated refresh (DRAM requires refresh less often at low temperatures), partial array self refresh, and a "deep power down" mode which sacrifices all memory contents. Additionally, chips are smaller, using less board space than their non-mobile equivalents. Samsung and Micron are two of the main providers of this technology, which is used in tablet computing devices such as the Apple iPad, Samsung Galaxy Tab and Motorola Droid X.[2]

LPDDR2[edit]

A new JEDEC standard JESD209-2E defines a more dramatically revised low-power DDR interface. It is not compatible with either DDR1 or DDR2 SDRAM, but can accommodate either:

  • LPDDR2-S2: 2n prefetch memory (like DDR1),
  • LPDDR2-S4: 4n prefetch memory (like DDR2), or
  • LPDDR2-N: Non-volatile (NAND flash) memory.

Low-power states are similar to basic LPDDR, with some additional partial array refresh options.

Timing parameters are specified for LPDDR-200 to LPDDR-1066 (clock frequencies of 100 to 533 MHz).

Working at 1.2 V, LPDDR2 multiplexes the control and address lines onto a 10-bit double data rate CA bus. The commands are similar to those of normal SDRAM, except for the reassignment of the precharge and burst terminate opcodes:

LPDDR2 command encoding[3]
CK CA0
(RAS)
CA1
(CAS)
CA2
(WE)
CA3 CA4 CA5 CA6 CA7 CA8 CA9 Operation
H H H NOP
H H L H H Precharge all banks
H H L H L BA2 BA1 BA0 Precharge one bank
H H L H A30 A31 A32 BA2 BA1 BA0 Preactive
(LPDDR2-N only)
A20 A21 A22 A23 A24 A25 A26 A27 A28 A29
H H L L Burst terminate
H L H reserved C1 C2 BA2 BA1 BA0 Read
(AP=auto-precharge)
AP C3 C4 C5 C6 C7 C8 C9 C10 C11
H L L reserved C1 C2 BA2 BA1 BA0 Write
(AP=auto-precharge)
AP C3 C4 C5 C6 C7 C8 C9 C10 C11
L H R8 R9 R10 R11 R12 BA2 BA1 BA0 Activate
(R0–14=Row address)
R0 R1 R2 R3 R4 R5 R6 R7 R13 R14
L H A15 A16 A17 A18 A19 BA2 BA1 BA0 Activate
(LPDDR2-N only)
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14
L L H H Refresh all banks
(LPDDR2-Sx only)
L L H L Refresh one bank
(Round-robin addressing)
L L L H MA0 MA1 MA2 MA3 MA4 MA5 Mode register read
(MA0–7=Address)
MA6 MA7
L L L L MA0 MA1 MA2 MA3 MA4 MA5 Mode register write
(OP0–7=Data)
MA6 MA7 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7

Column address bit C0 is never transferred, and is assumed to be zero. Burst transfers thus always begin at even addresses.

LPDDR2 also has an active-low chip select (when high, everything is a NOP) and clock enable CKE signal, which operate like SDRAM. Also like SDRAM, the command sent on the cycle that CKE is first dropped selects the power-down state:

  • If the chip is active, it freezes in place.
  • If the command is a NOP (CS low or CA0–2 = HHH), the chip idles.
  • If the command is a refresh command (CA0–2 = LLH), the chip enters the self-refresh state.
  • If the command is a burst terminate (CA0–2 = HHL), the chip enters the deep power-down state. (A full reset sequence is required when leaving.)

The mode registers have been greatly expanded compared to conventional SDRAM, with an 8-bit address space, and the ability to read them back. Although smaller than a serial presence detect EEPROM, enough information is included to obviate the need for one.

S2 devices smaller than 4 Gbit, and S4 devices smaller than 1 Gbit have only 4 banks. They ignore the BA2 signal, and do not support per-bank refresh.

Non-volatile memory devices do not use the refresh commands, and reassign the precharge command to transfer address bits A20 and up. The low-order bits (A19 and down) are transferred by a following Activate command. This transfers the selected row from the memory array to one of 4 or 8 (selected by the BA bits) row data buffers, where they can be read by a Read command. Unlike DRAM, the bank address bits are not part of the memory address; any address can be transferred to any row data buffer. A row data buffer may be from 32 to 4096 bytes long, depending on the type of memory. Rows larger than 32 bytes ignore some of the low-order address bits in the Activate command. Rows smaller than 4096 bytes ignore some of the high-order address bits in the Read command.

Non-volatile memory does not support the Write command to row data buffers. Rather, a series of control registers in a special address region support Read and Write commands, which can be used to erase and program the memory array.

LPDDR3[edit]

In May 2012, JEDEC published the JESD209-3 Low Power Memory Device Standard.[4][5][6] In comparison to LPDDR2, LPDDR3 offers a higher data rate, greater bandwidth and power efficiency, and higher memory density. LPDDR3 achieves a data rate of 1600 MT/s and utilizes key new technologies: write-leveling and command/address training,[7] optional on-die termination (ODT), and low-I/O capacitance. LPDDR3 supports both package-on-package (PoP) and discrete packaging types.

The command encoding is identical to LPDDR2, using a 10-bit double data rate CA bus.[5] However, the standard only specifies 8n-prefetch DRAM, and does not include the flash memory commands.

Products using LPDDR3 include the 2013 Macbook Air, iPhone 5S, Nexus 10 and Samsung Galaxy S4 (GT-I9500).[8] LPDDR3 went mainstream in 2013, running at 800 MHz DDR (1600 MT/s), offering bandwidth comparable to PC3-12800 notebook memory in 2011 (12.8 GB/s of bandwidth).[9] However, even though it offers the same memory bandwidth as notebook memory from 2011. To achieve this bandwidth, the controller must implement dual-channel memory. For example, this is the case for the Exynos 5 Dual[10] and the 5 Octa.[11]

Samsung Electronics introduced the first 4 Gigabit 20 nm-class LPDDR3 modules capable of transmitting data at up to 2,133 Mbit/s per pin, more than double the performance of the older LPDDR2 which is only capable of 800 Mbit/s.[12] Various SoCs from various manufacturers also natively support 800 MHz LPDDR3 RAM. Such include the Snapdragon 600 and 800 from Qualcomm[13] as well as some SoCs from the Exynos and Allwinner series.

LPDDR4[edit]

On March 14, 2012, JEDEC hosted a conference to explore how future mobile device requirements will drive upcoming standards like LPDDR4.[14] On December 30, 2013, Samsung announced that it has developed the first 20 nm-class 8 Gigabit (1GB) LPDDR4 capable of transmitting data at 3,200 Mbit/s, thus providing 50 percent higher performance than the fastest LPDDR3 and consuming around 40 percent less energy at 1.1 volts.[15]

References[edit]

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