NVM Express, NVMe, or Non-Volatile Memory Host Controller Interface Specification (NVMHCI), is a specification for accessing solid-state drives (SSDs) attached through the PCI Express (PCIe) bus. NVM is an acronym for non-volatile memory, as used in SSDs.
A major application of NVMe is SATA Express, which is a new and backward-compatible interface specification supporting either SATA or PCI Express storage devices. SATA Express can use either legacy AHCI or new NVMe as the logical device interface.
Historically, most SSDs used buses such as SATA, SAS or Fibre Channel for interfacing with the rest of a computer system. Since the SSDs became available in mass markets, SATA has been the most typical way for connecting SSDs in personal computers; however, SATA was designed for mechanical hard disk drives, and has become increasingly inadequate as SSDs have improved. For example, unlike hard disk drives, some SSDs are limited by the maximum throughput of SATA.
High-end SSDs have been made using the PCI Express bus before, but using non-standard specification interfaces. By standardizing the interface of SSDs, operating systems only need one driver to work with all SSDs adhering to the specification. It also means that each SSD manufacturer does not have to use additional resources to design specific interface drivers. This is similar to how USB mass storage devices are built to follow the USB mass storage device class specification and work with all computers, with no per-device drivers needed.
The first details of a new standard for accessing non-volatile memory emerged at the Intel Developer Forum 2007, when NVMHCI was shown as the host-side protocol of a proposed architectural design that had ONFI on the memory (flash) chips side. A NVMHCI working group led by Intel was formed that year. The NVMHCI 1.0 specification was completed in April 2008 and released on Intel's web site.
Technical work on NVMe began in the second half of 2009. The NVMe specifications were developed by the NVM Express Workgroup, which consists of more than 90 companies; Amber Huffman of Intel was the working group's chair. Version 1.0 of the specification was released on 1 March 2011, while version 1.1 of the specification was released on 11 October 2012. Major features added in version 1.1 are multi-path I/O (with namespace sharing) and arbitrary-length scatter-gather I/O. It is expected that future revisions will significantly enhance namespace management. Because of its feature focus, NVMe 1.1 was initially called "Enterprise NVMHCI". An update for the base NVMe specification, called version 1.0e, was released in January 2013.
In June 2011, a Promoter Group led by seven companies was formed. Cisco, Dell, EMC, IDT, Intel, NetApp, and Oracle have permanent seats in this group, while six other seats are held by representatives elected from the other member companies of the workgroup.
The first commercially available NVMe chipsets were released by Integrated Device Technology (89HF16P04AG3 and 89HF32P08AG3) in August 2012. The first NVMe drive, Samsung's XS1715 enterprise drive, was announced in July 2013; according to Samsung, this drive supported 3 GB/s read speeds, six times faster than their previous enterprise offerings. The LSI SandForce SF3700 controller family, released in November 2013, also supports NVMe. Sample engineering boards with the PCI Express 2.0 ×4 model of this controller found 1,800 MB/sec read/write sequential speeds and 150K/80K random IOPS. A Kingston HyperX "prosumer" product using this controller was showcased at the Consumer Electronics Show 2014 and promised similar performance. As of March 2014, none of the announced NVMe drives are commercially available.
Comparison with AHCI
While Advanced Host Controller Interface (AHCI) interface has the benefit of legacy software compatibility, it does not deliver optimal performance when an SSD is connected via PCI Express bus. This is because AHCI was developed back at the time when the purpose of a host bus adapter (HBA) in a system was to connect the CPU/memory subsystem with a much slower storage subsystem based on rotating magnetic media. Such an interface has some inherent inefficiencies when applied to SSD devices, which behave much more like DRAM than like spinning media.
NVMe has been designed from the ground up, capitalizing on the low latency and parallelism of PCI Express SSDs, and fulfilling the parallelism of contemporary CPUs, platforms and applications. At a high level, the basic advantages of NVMe over AHCI relate to its ability to exploit parallelism in host hardware and software, manifested by differences in depth of command queues, interrupts processing, the number of uncacheable register accesses etc., resulting in various performance improvements.:p. 17–18
The table below summarizes high-level differences between the basic NVMe and AHCI device interfaces.
|Maximum queue depth||1 command queue;
32 commands per queue
65536 commands per queue
|Uncacheable register accesses
(2000 cycles each)
|6 per non-queued command;
9 per queued command
|2 per command|
and interrupt steering
|2048 MSI-X interrupts|
and multiple threads
|requires synchronization lock
to issue a command
for 4 KB commands
|command parameters require
two serialized host DRAM fetches
|gets command parameters
in one 64 Bytes fetch
Operating system support
- The "NVMe Windows Working Group" is an initiative from the OpenFabrics Alliance to maintain software for Microsoft Windows to use PCI Express solid state devices. The baseline Windows driver contributed to the open-source initiative was developed by several promoter companies in the NVMe workgroup, specifically IDT, Intel, and LSI.
- Intel published an NVM Express driver for Linux. It was merged into the Linux kernel mainline on 19 March 2012, with the release of version 3.3 of the Linux kernel.
- A scalable block layer for high-performance SSD storage, developed primarily by Fusion-io engineers, was merged into the Linux kernel mainline in kernel version 3.13, released on 19 January 2014. This leverages the performance offered by SSDs and NVM Express, by allowing much higher I/O submission rates. With this new design of the Linux kernel block layer, internal queues are split into two levels (per-CPU and hardware-submission queues), thus removing bottlenecks and allowing much higher levels of I/O parallelization. With the release of Linux kernel version 3.13, only the virtioblk driver has been modified to actually use this new interface; other drivers will be ported in the following releases.
- Development work required to support NVMe in OpenBSD has been started in April 2014 by a senior developer formerly responsible for USB 2.0 and AHCI support.
- M.2 (connector and card format specification, supporting either SATA or PCI Express storage devices)
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