National Semiconductor SC/MP
It features a 16-bit address and an 8-bit data bus. The program counter will roll-over on 12-bits (4096), there are separate instructions to alter the program counter to set the upper 4-bits, which are subsequently output on the address bus along with status signals. This provides a memory map of 16 pages each of 4 KB. Internally it provided five registers plus the program counter, but no stack pointer.
SC/MP unusual features
An advanced and unusual feature for the time, is the ability to release the buses, so that they can be shared by multiple processors. The linked datasheet shows an implementation with three SC/MP in a multi-processor configuration.
SC/MP increments the program counter before fetching the instruction, so that on reset it actually starts executing instructions from location 0001. This also needs to be taken into account for calculating displacements, since the offset will be added to the program counter which will be still pointing to the location of the displacement and not the next instruction.
To minimize chip count in control applications it has dedicated serial input and output pins to allow implementation of serial communications in software without the need for a UART (this feature was removed in the later SC/MP III).
INS 8050 ISP-8A/500 SC/MP-1 Clocked at 1 MHz, first implementation (P Channel MOS technology)
INS 8060 ISP-8A/600 SC/MP-2 Clocked at 4 MHz (internally 2 MHz) first N Channel MOS version (single +5V supply)
INS 807x SC/MP-3 Clocked at 4 MHz (internally 2 MHz) included variations with up to 4 KB ROM (optional onboard BASIC (NIBL))