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In telecommunication, a non-return-to-zero (NRZ) line code is a binary code in which 1s are represented by one significant condition (usually a positive voltage) and 0s are represented by some other significant condition (usually a negative voltage), with no other neutral or rest condition. The pulses have more energy than a return-to-zero (RZ) code. Unlike RZ, NRZ does not have a rest state. NRZ is not inherently a self-clocking signal, thus some additional synchronization technique (for example a run length limited constraint, or a parallel synchronization signal) must be used for avoiding bit slip.
When used to represent data in an asynchronous communication scheme, the absence of a neutral state requires other mechanisms for bit synchronization when a separate clock signal is not available.
NRZ-Level itself is not a synchronous system but rather an encoding that can be used in either a synchronous or asynchronous transmission environment, that is, with or without an explicit clock signal involved. Because of this, it is not strictly necessary to discuss how the NRZ-Level encoding acts "on a clock edge" or "during a clock cycle" since all transitions happen in the given amount of time representing the actual or implied integral clock cycle. The real question is that of sampling—the high or low state will be received correctly provided the transmission line has stabilized for that bit when the physical line level is sampled at the receiving end.
However, it is helpful to see NRZ transitions as happening on the trailing (falling) clock edge in order to compare NRZ-Level to other encoding methods, such as the mentioned Manchester code, which requires clock edge information (is the XOR of the clock and NRZ, actually) see the difference between NRZ-Mark and NRZ-Inverted.
Unipolar non-return-to-zero level
"One" is represented by one physical level (such as a DC bias on the transmission line).
"Zero" is represented by another level (zero volts in unipolar case).
In clock language, "one" transitions or remains high on the trailing clock edge of the previous bit and "zero" transitions or remains low on the trailing clock edge of the previous bit, or just the opposite. This allows for long series without change, which makes synchronization difficult. One solution is to not send bytes without transitions. Disadvantages of an on-off keying are the waste of power due to the transmitted DC level and the power spectrum of the transmitted signal does not approach zero at zero frequency. See RLL
Bipolar non-return-to-zero level
"One" is represented by one physical level (usually a positive voltage).
"Zero" is represented by another level (usually a negative voltage).
In clock language, in bipolar NRZ-Level the voltage "swings" from positive to negative on the trailing edge of the previous bit clock cycle.
An example of this is RS-232, where "one" is −12 V to −5 V and "zero" is +5 V to +12 V.
"One" is represented by no change in physical level.
"Zero" is represented by a change in physical level.
In clock language, the level transitions on the trailing clock edge of the previous bit to represent a "zero."
This "change-on-zero" is used by High-Level Data Link Control and USB. They both avoid long periods of no transitions (even when the data contains long sequences of 1 bits) by using zero-bit insertion. HDLC transmitters insert a 0 bit after five contiguous 1 bits (except when transmitting the frame delimiter '01111110'). USB transmitters insert a 0 bit after six consecutive 1 bits. The receiver at the far end uses every transition — both from 0 bits in the data and these extra non-data 0 bits — to maintain clock synchronization. The receiver otherwise ignores these non-data 0 bits.
Non return to zero, inverted (NRZI) is a method of mapping a binary signal to a physical signal for transmission over some transmission media. The two level NRZI signal has a transition at a clock boundary if the bit being transmitted is a logical 1, and does not have a transition if the bit being transmitted is a logical 0.
"One" is represented by a transition of the physical level.
"Zero" has no transition.
Also, NRZI might take the opposite convention, as in Universal Serial Bus (USB) signalling, when in Mode 1, in which a transition occurs when signaling zero, and a steady level when signaling a one.
The transition occurs on the leading edge of the clock for the given bit. This distinguishes NRZI from NRZ-Mark.
However, even NRZI can have long series of zeros (or ones if transitioning on "zero"), and thus clock recovery can be difficult unless some form of run length limited (RLL) coding is used in addition to NRZI. Magnetic disk and tape storage devices generally use fixed-rate RLL codes, while USB uses bit stuffing, which inserts an additional 0 bit after 6 consecutive 1 bits, thus forcing a transition. While bit stuffing is efficient, it results in a variable data rate because it takes slightly longer to send a long string of 1 bits than it does to send a long string of 0 bits.
|Wikimedia Commons has media related to Non return to zero.|
- Bipolar encoding
- Enhanced Non-Return-to-Zero-Level E-NRZ-L
- Line code
- Universal asynchronous receiver/transmitter
- Manchester code
- Brey, Barry. The Intel Microprocessors, Columbus: Pearson Prentice Hall. ISBN 0-13-119506-9