Op amp integrator

The operational amplifier integrator is an electronic integration circuit. Based around the operational amplifier (op-amp), it performs the mathematical operation of integration with respect to time; that is, its output voltage is proportional to the input voltage integrated over time.

Applications

The integrator circuit is mostly used in analog computers, analog-to-digital converters and wave-shaping circuits. A common wave-shaping use is as a charge amplifier and they are usually constructed using an operational amplifier though they can use high gain discrete transistor configurations.

Design

The input current is offset by a negative feedback current flowing in the capacitor, which is generated by an increase in output voltage of the amplifier. The output voltage is therefore dependent on the value of input current it has to offset and the inverse of the value of the feedback capacitor. The greater the capacitor value, the less output voltage has to be generated to produce a particular feedback current flow.

The input impedance of the circuit is almost zero because of the Miller effect. Hence all the stray capacitances (the cable capacitance, the amplifier input capacitance, etc.) are virtually grounded and they have no influence on the output signal.[1]

Ideal circuit

The circuit operates by passing a current that charges or discharges the capacitor Cf during the time under consideration, which strives to retain the virtual ground condition at the input by off-setting the effect of the input current. Referring to the above diagram, if the op-amp is assumed to be ideal, nodes v1 and v2 are held equal, and so v2 is a virtual ground. The input voltage passes a current $\frac{v_{in}}{R_1}$ through the resistor producing a compensating current flow through the series capacitor to maintain the virtual ground. This charges or discharges the capacitor over time. Because the resistor and capacitor are connected to a virtual ground, the input current does not vary with capacitor charge and a linear integration of output is achieved.

The circuit can be analyzed by applying Kirchhoff's current law at the node v2, keeping ideal op-amp behaviour in mind.

$i_{\text{1}} = I_{\text{B}} + i_{\text{F}}$

$I_{\text{B}} = 0$ in an ideal op-amp, so:

$i_{\text{1}} = i_{\text{F}}$

Furthermore, the capacitor has a voltage-current relationship governed by the equation:

$I_{\text{C}} = C \frac{dV_{\text{c}}}{dt}$

Substituting the appropriate variables:

$\frac{v_{\text{in}} - v_{\text{2}}}{R_{\text{1}}} = C_{\text{F}}\frac{d(v_{\text{2}} - v_{\text{o}})}{dt}$

$v_2 = v_1 = 0$ in an ideal op-amp, resulting in:

$\frac{v_{\text{in}}}{R_{\text{1}}} = -C_{\text{F}}\frac{dv_{\text{o}}}{dt}$

Integrating both sides with respect to time:

$\int_0^t\frac{v_{\text{in}}}{R_{\text{1}}} \ dt\ = - \int_0^t C_{\text{F}} \frac{dv_{\text{o}}}{dt} \, dt$

If the initial value of vo is assumed to be 0 V, this results in a DC error of:[2]

$v_{\text{o}} = -\frac{1}{R_{\text{1}}C_{\text{F}}}\int_0^t v_{\text{in}}\, dt$

Practical circuit

The ideal circuit is not a practical integrator design for a number of reasons. Practical op-amps have a finite open-loop gain, an input offset voltage and input bias currents ($I_B$). This can cause several issues for the ideal design; most importantly, if $v_{\text{in}} = 0$, both the output offset voltage and the input bias current $I_B$ can cause current to pass through the capacitor, causing the output voltage to drift over time until the op-amp saturates. Similarly, if $v_{\text{in}}$ were a signal centered about zero volts (i.e. without a DC component), no drift would be expected in an ideal circuit, but may occur in a real circuit. To negate the effect of the input bias current, it is necessary to set:

$R_{\text{on}}=R_1 || R_f || R_L$. The error voltage then becomes:

$V_\text{E} = \left( \frac{R_\text{f}}{R_1} + 1 \right) V_{IOS}$

The input bias current thus causes the same voltage drops at both the positive and negative terminals.

Also, in a DC steady state, the capacitor acts as an open circuit. The DC gain of the ideal circuit is therefore infinite (or in practice, the open-loop gain of a non-ideal op-amp). To counter this, a large resistor $R_F$ is inserted in parallel with the feedback capacitor, as shown in the figure above. This limits the DC gain of the circuit to a finite value, and hence changes the output drift into a finite, preferably small, DC error. Referring to the above diagram:

$V_\text{E} = \left( \frac{R_\text{f}}{R_1} + 1 \right) \left( V_{IOS} + I_{BI} \left( R_\text{f} \parallel R_1 \right) \right)$

where $V_{IOS}$ is the input offset voltage and $I_{BI}$ is the input bias current on the inverting terminal. $R_f \parallel R_1$ indicates two resistance values in parallel.

Frequency response

The frequency responses of the practical and ideal integrator are shown in the above figure. For both circuits, the crossover frequency $f_\text{b}$, at which the gain is 0 dB, is given by:

$f_{\text{b}}=\frac{1}{{2\pi}{R_{\text{1}}}{ C_{\text{F}}}}$

The 3 dB cutoff frequency $f_\text{a}$ of the practical circuit is given by:

$f_{\text{a}}=\frac{1}{{2\pi}{R_{\text{F}}}{ C_{\text{F}}}}$

The practical integrator circuit is equivalent to an active first-order low-pass filter. The gain is relatively constant up to the cutoff frequency and decreases by 20 dB per decade beyond it. The integration operation occurs for frequencies in the range $\left[ f_\text{a}, f_\text{b} \right]$, provided that $f_\text{a} < f_\text{b}$. This condition can be achieved by appropriate choice of $R_\text{F}C_\text{F}$ and $R_1 C_\text{F}$ time constants.

References

1. ^ Transducers with Charge Output
2. ^ "AN1177 Op Amp Precision Design: DC Errors" (PDF). Microchip. 2 January 2008. Archived from the original on 2013-01-11. Retrieved 26 December 2012.