The PDP-11 was a series of 16-bit minicomputers sold by Digital Equipment Corporation (DEC) from 1970 into the 1990s, one of a succession of products in the PDP series. The PDP-11 replaced the PDP-8 in many real-time applications, although both product lines lived in parallel for more than 10 years. The PDP-11 had several uniquely innovative features, and was easier to program than its predecessors with its use of general registers. Its successor in the mid-range minicomputer niche was the 32-bit VAX-11.
Design features of the PDP-11 influenced the design of microprocessors such as the Motorola 68000; design features of its operating systems, as well as other operating systems from Digital Equipment, influenced the design of other operating systems such as CP/M and hence also MS-DOS. The first officially named version of Unix ran on the PDP-11/20 in 1970. It is commonly stated that the C programming language took advantage of several low-level PDP-11–dependent programming features, albeit not originally by design.
DEC developed the 16-bit PDP 11 as a response to the introduction of the Data General NOVA, which had a 16-bit word length; DEC's previous PDP-8 had only 12 bit words. The PDP 11 family was announced in January 1970 and shipments began early that year. DEC sold over 170,000 PDP-11s in the 1970s. Initially manufactured of small-scale Transistor–transistor logic, a single-board large scale integration version of the processor was developed in 1975. A single-chip processor, the J-11 was developed in 1979. The last models of the PDP-11 line were the PDP-11/94 and -11/93 introduced in 1990.
Instruction set orthogonality
The PDP-11 processor architecture had a mostly orthogonal instruction set. For example, instead of instructions such as load and store, the PDP-11 had a move instruction for which either operand (source and destination) could be memory or register. There were no specific input or output instructions; the PDP-11 used memory-mapped I/O and so the same move instruction was used; orthogonality even enabled moving data directly from an input device to an output device. More complex instructions such as add likewise could have memory, register, input, or output as source or destination.
Most operands could apply any of eight addressing modes to eight registers. The addressing modes provided register, immediate, absolute, relative, deferred (indirect), and indexed addressing, and could specify autoincrementation and autodecrementation of a register by one (byte instructions) or two (word instructions). Use of relative addressing let a machine-language program be position-independent.
No dedicated I/O instructions
An input/output device determined the memory addresses to which it would respond, and specified its own interrupt vector and interrupt priority. This flexible framework provided by the processor architecture made it unusually easy to invent new bus devices, including devices to control hardware that had not been contemplated when the processor was originally designed. DEC openly published the basic Unibus specifications, even offering prototyping bus interface circuit boards, and encouraging customers to develop their own Unibus-compatible hardware.
The Unibus made the PDP-11 suitable for custom peripherals. One of the predecessors of Alcatel-Lucent, the Bell Telephone Manufacturing Company, developed the BTMC DPS-1500 packet-switching (X.25) network and used PDP-11s in the regional and national network management system, with the Unibus directly connected to the DPS-1500 hardware.
Higher-performance members of the PDP-11 family, starting with the PDP-11/45 Unibus and 11/83 Q-bus systems, departed from the single-bus approach. Instead, memory was interfaced by dedicated circuitry and space in the CPU cabinet, while the Unibus continued to be used for I/O only. In the PDP-11/70, this was taken a step further, with the addition of a dedicated interface between disks and tapes and memory, via the Massbus. Although input/output devices continued to be mapped into memory addresses, some additional programming was necessary to set up the added bus interfaces.
The PDP-11 supported hardware interrupts at four priority levels. Interrupts were serviced by software service routines, which could specify whether they themselves could be interrupted (achieving interrupt nesting). The event that caused the interrupt was indicated by the device itself, as it informed the processor of the address of its own interrupt vector.
Interrupt vectors were blocks of two 16-bit words in low kernel address space (which normally corresponded to low physical memory) between 0 and 776. The first word of the interrupt vector contained the address of the interrupt service routine and the second word the value to be loaded into the PSW (priority level) on entry to the service routine.
The article on PDP-11 architecture provides more details on interrupts.
Designed for mass production
The PDP-11 was designed for ease of manufacture by semiskilled labor. The dimensions of its pieces were relatively non-critical. It used a wire-wrapped backplane. That is, the printed circuit boards plugged into a backplane connector. The backplane connectors had square pins that could be connected to by wrapping wires around them. The corners of the pins would bite into the wire to form a gas-tight (i.e. corrosion-proof, therefore reliable) connection.
The LSI-11 (PDP-11/03), introduced in February, 1975 was the first PDP-11 model produced using large-scale integration; the entire CPU was contained on four LSI chips made by Western Digital (the MCP-1600 chip set; a fifth chip could be added to extend the instruction set, as pictured on the right). It used a bus which was a close variant of the Unibus called the LSI Bus or Q-Bus; it differed from the Unibus primarily in that addresses and data were multiplexed onto a shared set of wires, as opposed to having separate sets of wires, as in the Unibus. It also differed slightly in how it addressed I/O devices and it eventually allowed a 22-bit physical address (whereas the Unibus only allowed an 18-bit physical address) and block-mode operations for significantly improved bandwidth (which the Unibus did not support).
The CPU's microcode includes a debugger: firmware with a direct serial interface (RS-232 or current loop) to a terminal. This let the operator do debugging by typing commands and reading octal numbers, rather than operating switches and reading lights, the typical debugging method at the time. The operator could thus examine and modify the computer's registers, memory, and input/output devices, diagnosing and perhaps correcting failures in software and peripherals (unless a failure disabled the microcode itself). The operator could also specify which disk to boot from.
Both innovations increased the reliability and decreased the cost of the LSI-11.
Later Q-Bus based systems such as the LSI-11/23, /73, and /83 were based upon chip sets designed in house by Digital Equipment Corporation. Later PDP-11 Unibus systems were designed to use similar Q-Bus processor cards, using a Unibus adapter to support existing Unibus peripherals, sometimes with a special memory bus for improved speed.
There were other significant innovations in the Q-Bus lineup. For example, a system variant of the PDP-11/03 introduced full system Power-On Self-Test (POST).
The basic design of the PDP-11 was flexible, and was continually updated to use newer technologies. However, the limited throughput of the Unibus and Q-bus started to become a system-performance bottleneck, and the 16-bit logical address limitation hampered the development of larger software applications. The article on PDP-11 architecture describes the hardware and software techniques used to work around address-space limitations.
DEC's 32-bit successor to the PDP-11, the VAX (for "Virtual Address eXtension") overcame the 16-bit limitation, but was initially a superminicomputer aimed at the high-end time-sharing market. The early VAXes provided a PDP-11 compatibility mode under which much existing software could be immediately used, in parallel with newer 32-bit software.
In the 1980s, the IBM PC and its clones largely took over the small computer market, and DEC was unable to counter this competition.
Newer microprocessor chips such as the Motorola 68000 (1979) and Intel 80386 (1985) also included 32-bit logical addressing. The mass-production of those chips eliminated any cost advantage for the 16-bit PDP-11. A line of personal computers based on the PDP-11, the DEC Professional series, failed commercially, along with other non-PDP-11 PC offerings from DEC.
In 1994 DEC  sold the PDP-11 system-software rights to Mentec Inc., an Irish producer of LSI-11 based boards for Q-Bus and ISA architecture personal computers, and in 1997 discontinued PDP-11 production. For several years, Mentec produced new PDP-11 processors. Other companies found a niche market for replacements for legacy PDP-11 processors, disk subsystems, etc.
By the late 1990s, not only DEC but most of the New England computer industry which had been built around minicomputers similar to the PDP-11 collapsed in the face of microcomputer-based workstations and servers.
The PDP-11 processors tended to fall into several natural groups depending on the original design upon which they are based and which I/O bus they used. Within each group, most models were offered in two versions, one intended for OEMs and one intended for end-users. Although all models shared the same instruction set, later models added new instructions and interpreted certain instructions slightly differently. As the architecture evolved, there were also variations in handling of some processor status and control registers.
The following models used the Unibus as their principal bus:
- PDP-11/20 and PDP-11/15 — The original, non-microprogrammed processor; designed by Jim O'Loughlin. Floating point was supported by peripheral options using various data formats.
- PDP-11/35 and PDP-11/40 — A microprogrammed successor to the PDP-11/20; the design team was led by Jim O'Loughlin.
- PDP-11/45, PDP-11/50, and PDP-11/55 — A much faster microprogrammed processor that could use up to 256 kB of semiconductor memory instead of or in addition to core memory. First model to support an optional FP11 floating-point coprocessor, which established the format used in later models.
- PDP-11/70 — The 11/45 architecture expanded to allow 4 MB of physical memory segregated onto a private memory bus, 2 kB of cache memory, and much faster I/O devices connected via the Massbus.
- PDP-11/05 and PDP-11/10 — A cost-reduced successor to the PDP-11/20.
- PDP-11/34 and PDP-11/04 — Cost-reduced follow-on products to the 11/35 and 11/05; the PDP-11/34 concept was created by Bob Armstrong. The 11/34 supported up to 256 kB of Unibus memory. The PDP-11/34a supported a fast floating-point option, and the 11/34c supported a cache memory option.
- PDP-11/60 — A PDP-11 with user-writable microcontrol store; this was designed by another team led by Jim O'Loughlin.
- PDP-11/44 — A replacement for the 11/45 and 11/70, introduced in 1980, that supported optional (though apparently always included) cache, memory, FP-11 floating-point processor (one circuit board, using sixteen AMD Am2901 bit slice processors), and commercial instruction set (CIS, two boards). It included a sophisticated serial console interface and support for 4 MB of physical memory. The design team was managed by John Sofio. This was the last PDP-11 processor to be constructed using discrete logic gates; later models were all microprogrammed. It was also the last model produced at Digital Equipment Corporation.
- PDP-11/24 — First VLSI PDP-11 for Unibus, using the "Fonz-11" (F11) chip set with a Unibus adapter.
- PDP-11/84 — Using the VLSI "Jaws-11" (J11) chip set with a Unibus adapter.
- PDP-11/94 — J11-based, faster than 11/84.
The following models used the Q-Bus as their principal bus:
- PDP-11/03 (also known as the LSI-11/03) — The first LSI PDP-11, this system used a chipset from Western Digital and supported 60 kB of memory.
- PDP-11/23 — Second generation of LSI (F-11). Early units supported only 248 kB of memory.
- PDP-11/23+/MicroPDP-11/23 — Improved 11/23 with more functions on the (larger) processor card.
- MicroPDP-11/73 — The third generation LSI-11, this system used the faster "Jaws-11" (J-11) chip set and supported up to 4 MB of memory.
- MicroPDP-11/53 — Slower 11/73 with on-board memory.
- MicroPDP-11/83 — Faster 11/73 with PMI (private memory interconnect).
- MicroPDP-11/93 — Faster 11/83; final DEC Q-Bus PDP-11 model.
- KXJ11 - QBUS card (M7616) with PDP-11 based peripheral processor and DMA controller. Based on a J11 CPU equipped with 512 kB of RAM, 64 kB of ROM, and parallel and serial interfaces.
- Mentec M100 — Mentec redesign of the 11/93, with J-11 chipset at 19.66 MHz, four on-board serial ports, 1-4 MB of on-board memory, and optional FPU.
- Mentec M11 — Processor upgrade board; microcode implementation of PDP-11 instruction set by Mentec, using the TI 8832 ALU and TI 8818 microsequencer from Texas Instruments.
- Mentec M1 — Processor upgrade board; microcode implementation of PDP-11 instruction set by Mentec, using Atmel 0.35 μm ASIC.
- Quickware QED-993 — High performance PDP-11/93 processor upgrade board.
- DECserver 500 and 550 LAT terminal servers DSRVS-BA using the KDJ11-SB chipset
Models without standard bus
The PDT series were desktop systems marketed as "smart terminals". The /110 and /130 were housed in a VT100 terminal enclosure. The /150 was housed in a table-top unit which included two 8 inch floppy drives, three asynchronous serial ports, one printer port, one modem port and one synchronous serial port and required an external terminal. All three employed the same chipset as used on the LSI-11/03 and LSI-11/2 in four "microm"s. There was an option which combined two of the microms into one dual carrier, freeing one socket for an EIS/FIS chip. The /150 in combination with a VT105 terminal was also sold as MiniMINC, a budget version of the MINC-11.
The DEC Professional series were desktop PCs intended to compete with IBM's earlier 8088 and 80286 based personal computers. The models were equipped with 5¼ inch floppy disk drives and hard disks, except the 325 which had no hard disk. The original operating system was P/OS, which was essentially RSX-11M+ with a menu system on top. As the design was intended to avoid software exchange with existing PDP-11 models, their ill fate in the market was no surprise for anyone except DEC. The RT-11 was eventually ported to the PRO series. A port to the PRO for RSTS/E was also done internal to DEC, but was not released. The PRO-325 and -350 units were based on the DCF-11 ("Fonz") chipset, the same as found in the 11/23, 11/23+ and 11/24. The PRO-380 was based on the DCJ-11 ("Jaws") chipset, the same as found in the 11/53,73,83 and others, though running only at 10 MHz because of limitations in the support chipset.
Models that were planned but never introduced
- PDP-11/27 — A Jaws-11 implementation that would have used the VAXBI Bus as its principal I/O bus.
- PDP-11/68 — A follow-on to the PDP-11/60 that would have supported 4 MB of physical memory.
- PDP-11/74 — A PDP-11/70 that was extended to contain multiprocessing features. Up to four processors could be interconnected, although the physical cable management became unwieldy. Another variation on the 11/74 contained both the multiprocessing features and the Commercial Instruction Set. A substantial number of prototype 11/74's (of various types) were built and at least two multiprocessor systems were sent to customers for beta testing, but no systems were ever officially sold. A four processor system was maintained by the RSX-11 operating system development team for testing and a uniprocessor system served PDP-11 engineering for general purpose timesharing. The 11/74 was due to be introduced around the same time as the announcement of the new 32-bit product line and the first model: the VAX 11/780. The 11/74 was cancelled because of concern for its field maintainability, though employees believed the real reason was that it outperformed the 11/780 (see, for example ) and would inhibit its sales. In any case, DEC never entirely migrated its PDP-11 customer base to the VAX. The primary reason was not performance, but the PDP-11's superior real-time responsiveness.
Special purpose versions
- GT40 — VT11 vector graphics terminal using a PDP-11/05.
- GT42 — VT11 vector graphics terminal using a PDP-11/10.
- GT44 — VT11 vector graphics terminal using a PDP-11/40.
- GT62 — VS60 vector graphics workstation using a PDP-11/34a.
- H11 — Heathkit OEM version of the LSI-11/03.
- VT20 — Terminal with PDP-11/05 with direct mapped character display for text editing and typesetting (predecessor of the VT71)
- VT71 — Terminal with LSI-11/03 and QBUS backplane with direct mapped character display for text editing and typesetting.
- VT103 — VT100 with backplane to host an LSI-11.
- VT173 — A high-end editing terminal containing an 11/03, which loaded its editing software over a serial connection to a host minicomputer. Used in various publishing environments, it was also offered with DECset, Digital's VAX/VMS 3.x native mode OEM version of the Datalogics Pager automated batch composition engine. When VT173 inventory was exhausted in 1985, Digital discontinued DECset and transferred its customer agreements to Datalogics. (HP now uses the name HP DECset for a software development toolset product.)
- MINC-11 — Laboratory system based on 11/03 or 11/23; when based on the 11/23, it was sold as a 'MINC-23', but many MINC-11 machines were field-upgraded with the 11/23 processor. Early versions of the MINC-specific software package would not run on the 11/23 processor because of subtle changes in the instruction set; MINC 1.2 is documented as compatible with the later processor.
- C.mmp — Multiprocessor system from Carnegie Mellon University.
- SBC 11/21 (boardname KXT11) Falcon and Falcon Plus — single board computer on a Qbus card implementing the basic PDP-11 instruction set, based on T11 chipset containing 32 KB static RAM, two ROM sockets, three serial lines, 20 bit parallel I/O, three interval timers and a two-channel DMA controller. Up to 14 Falcons could be placed into one Qbus system.
- KXJ11 — QBUS card (M7616) with PDP-11 based peripheral processor and DMA controller. Based on a J11 CPU equipped with 512 kB RAM, 64 kB ROM and parallel and serial interfaces.
- HSC high end CI disk controllers used backplane mounted J11 and F11 processor cards to run their CHRONIC operating system.
The PDP-11 was sufficiently popular that many unauthorized PDP-11-compatible minicomputers and microcomputers were produced in Eastern Bloc countries. At least some of these were pin-compatible with DEC's PDP-11s and could share peripherals and system software. These include:
- SM-4, SM-1420, SM-1600, Elektronika BK series, Elektronika 60, Elektronika 85, DVK and UKNC (in the Soviet Union).
- SM-4, SM-1420, IZOT-1016 and peripherals (in Bulgaria).
- MERA-60 in Poland.
- SM-1620, SM-1630 (in East Germany).
- SM-4, TPA-1140, TPA-1148, TPA-11/440 (in Hungary).
- CalData — Made in U.S., ran all DEC OS's
Several operating systems were available for the PDP-11
From third parties
- CR11 — punched card reader
- LA30/LA36 — DECwriter dot-matrix printing keyboard terminal
- LP11 — high speed line printer
- PC11 — high speed papertape reader/punch
- RA,RD series — fixed platter hard disk
- RK series — hard disk with exchangeable platter
- RL01/RL02 — hard disk with exchangeable platter
- RM,RP series — exchangeable multi-platter hard disk
- RX01/RX02 — 8 inch floppy disk
- TU11 — 9 track tape drive
- TU56 — DECtape block-addressed tape system
- VT05/VT50/VT52/VT100 — video display terminal
The PDP-11 family of computers was used for many purposes. It was used as a standard minicomputer for general-purpose computing, such as timesharing, scientific, educational, or business computing. Another common application was real-time process control and factory automation.
Some OEM models also were frequently used as embedded systems to control complex systems like traffic-light systems, medical systems, numerical controlled machining, or for network-management. An example of such use of PDP-11s was the management of the packet switched network Datanet 1. In the 1980s, the UK's air traffic control radar processing was conducted on a PDP 11/34 system known as PRDS - Processed Radar Display System at RAF West Drayton. The software for the Therac-25 medical linear particle accelerator also ran on a 32K PDP 11/23.
Another use was for storage of test programs for Teradyne ATE equipment, in a system known as the TSD (Test System Director). As such, they were in use until their software was rendered inoperable by the Year 2000 problem. The U.S. Navy used a PDP-11/34 to control its Multi-station Spatial Disorientation Device, a simulator used in pilot training, until 2007, when it was replaced by a PC-based emulator that could run the original PDP-11 software and interface with custom Unibus controller cards.
- Heathkit H11, a 1977 Heathkit personal computer based on the PDP-11
- MACRO-11, the PDP-11's native assembly language
- PL-11, a high-level assembler for the PDP-11 written at CERN
- SIMH, a multiple minicomputer architecture emulator written in portable C
- Bell; Gordon; Strecker, Bill (1975). "What We Learned From the PDP-11". microsoft.com. p. 139. Retrieved September 10, 2008.
- 16-bit "Timeline". microsoft.com. Retrieved September 2008.
- Ceruzzi, Paul (2003), A History of Modern Computing, MIT Press, p. 238, ISBN 978-0-262-53203-7, retrieved 5 August 2010
- Conner, Doug. "Father of DOS Still Having Fun at Microsoft". Micronews. Retrieved 5 August 2010.
- Bakyo, John. "DEC PDP-11, benchmark for the first 16/32 bit generation. (1970)" in Great Microprocessors of the Past and Present (V 13.4.0), Section Three, Part I. Accessed 2011-03-04
- "The Development of the C Language" in section More History, by Dennis M. Ritchie. Accessed August 5, 2011.
- Paul Cerruzi, A History of Modern Computing, MIT Press, 2003, ISBN 0-262-53203-4, page 199
- Press Release re transfer of Operating Systems
- 1 MB = 1024 KB
- Development Project Report
- Bruce Mitchell, Brian S. McCarthy (2005). "Multiprocessor FAQ". Machine Intelligence. Retrieved May 21, 2011.
- Binary Dinosaurs - Digital MINC-11
- EK-HSCMN-IN-002 HSC Controller Installation Manual
- Brinch Hansen, Per (1976), The Solo Operating System: A Concurrent Pascal Program, retrieved 22 June 2011.
- Leveson, Nancy G., and Clark S. Turner. "An Investigation of the Therac-25 Accidents." Computer July 1993: 18-41.
- Claremont, Bruce (February 2008). "PDP-11 Replacement Keeps the Navy’s MSDD Spinning". Retrieved May 2012.
- Aubert, J.J. et al (November 1974). "Experimental Observation of a Heavy Particle J".
- PDP11 processor handbook - PDP11/05/10/35/40, Digital Equipment Corporation, 1973
- PDP11 processor handbook - PDP11/04/34a/44/60/70, Digital Equipment Corporation, 1979
- Eckhouse, jr., Richard H.; Morris, L. Robert (1979), Microcomputer Systems Organization, Programming and Applications (PDP-11), Englewood Cliffs, New Jersey: Prentice-Hall, ISBN 0-13-583914-9
- Michael Singer, PDP-11. Assembler Language Programming and Machine Organization, John Wiley & Sons, NY: 1980.
|Wikimedia Commons has media related to: PDP-11|
- The PDP-11 FAQ
- Preserving the PDP-11 Series of 16-bit minicomputers
- Gordon Bell and Bill Strecker's 1975 paper, What We Learned From the PDP-11
- Further papers and links on Gordon Bell's site.
- The Fuzzball
- On LSI-11, RT-11, Megabytes of Memory and Modula-2/VRS by Günter Dotzel, ModulaWare.com - An article on Modula-2 compiler/linker synergy to overcome the PDP/LSI-11 address space limitations, published in DEC Professional: the magazine for DEC users, Professional Press, Spring House, PA. U.S.A., January 1986.
- dpuadweb.depauw.edu/dharms_web/pdp11/. A video from DePauw University demonstrating how to program a PDP-11/10.
- pdp11.co.uk Site focused the preservation and restoration of PDP-11 computers
- electronica-60.ucoz.com Site focussed on the Russian versions of PDP-11 computers
- PDP-11/70 CPU core and SoC, OpenCores page describing a complete PDP-11 system: a 11/70 CPU with memory management unit, but without floating point unit, a basic set of UNIBUS peripherals (DL11, LP11, PC11, RK11/RK05), a cache and memory controllers for SRAM and PSRAM on FPGA