PICA200 is a graphics processing unit (GPU) for embedded devices designed by Digital Media Professionals Inc. (DMP), a Japanese GPU design company. It was announced at SIGGRAPH 2005, and presented on SIGGRAPH 2006 conference. PICA is DMP's brand of graphics processors for embedded devices, scalable from portables up to high-performance arcade systems. PICA200 simply denotes a 200 MHz-clocked GPU from PICA family.
PICA200 has an instruction-programmable core (IPC) that gives it capability to change configuration based on demands for specific target system, which will manage with its 3D graphics engine. PICA200 supports second-generation DMPs proprietary MAESTRO graphics technology ("MAESTRO-2G") which includes OpenGL ES 1.1 API support, optional OpenGL ES 1.1 extensions pack and some DMP proprietary extensions which enable custom hardware-based shading algorithms such as procedural texturing, bidirectional reflectance distribution function (BRDF), Cook-Torrance specular highlights, polygon subdivision ("Geo Shader", aka. tessellation), soft shadow projection and per-vertex subsurface scattering (similar to two-sided lighting).
The 3D processing core of PICA200 consists of up to four programmable vertex pipelines that can be rearranged as four pixel pipelines. The number of IPCs and pipelines will depend on the target processor core and may change in the future.
For 2D graphics rendering there are two optional add-ons: the image post-processing module PICA-FBM ("Frame Buffer Object") that can be used as an anti-aliasing filter with support for some specific 2D functions and the vector graphics module PICA-VG ("Vector Graphics") as PICA-FBM extension.
PICA-FBM is also available as a standalone 2D graphics core. PICA-VG is a PICA-FBM are only available as optional addons.
PICA-VG also supports released Khronos OpenVG 1.0 API, released on July 18, 2005 which give it additional potential for vector graphics acceleration.
PICA200 and MAESTRO-2G is a further refinement of DMP's first-generation MAESTRO developed in DMP's proof-of-concept processor ULTRAY2000.
- 65 nm Single Core (max. clock frequency 400 MHz)
- Power consumption: 0.5-1.0 mW/MHz
- Frame Buffer max. 4095×4095 pixels
- Supported pixel formats: RGBA 4-4-4-4, RGB 5-6-5, RGBA 5-5-5-1, RGBA 8-8-8-8
- Vertex program (ARB_vertex_program)
- Render to Texture
- Bilinear texture filtering
- Alpha blending
- Full-scene anti-aliasing (2×2)
- Polygon offset
- 8-bit stencil buffer
- 24-bit depth buffer
- Single/Double/Triple buffer
- DMP's MAESTRO-2G technology
- per pixel lighting
- procedural texture
- refraction mapping
- subdivision primitive
- gaseous object rendering
- "Procedural texture generation unit and saving video memory". August 15, 2006.
- "[Page64] DMP Inc. PICA graphics core". EuroGraphics 2008, Crete. April 14–18, 2008.
- "Soft shadow projection and use of programmable vertex processor". August 15, 2006.
- "PICA200's OpenGL ES 1.1 support, core programming and optional addon modules". August 15, 2006.
- "OpenVG specification". July 28, 2005.
- "Press Release: DMP 3D Graphics IP core "PICA200" is adopted by Nintendo 3DS". Digital Media Professionals Inc. (DMP). June 21, 2010.[html] [pdf]
- "PICA 200 3D Graphics IP (product brochure)". Digital Media Professionals Inc. (DMP). June 11, 2010.
"PICA200 3D Graphics IP".
"PICA200 block diagram".
"SIGGRAPH 2006 - 日本発のGPUテクノロジー「PICA200」が公開". journal.mycom.co.jp. August 15, 2006.
"ニンテンドー3DSにDMPの3DグラフィックスIPコア「PICA200」が採用された理由". journal.mycom.co.jp. June 22, 2010.