PLL multibit

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A PLL multibit or multibit PLL is a phase-locked loop (PLL) which achieves improved performance compared to a unibit PLL by using more bits. Unibit PLLs use only the most significant bit (MSB) of each counter's output bus to measure the phase, while multibit PLLs use more bits.[1] PLLs are an essential component in telecommunications.

Multibit PLLs achieve improved efficiency and performance: better utilization of the frequency spectrum, to serve more users at a higher quality of service (QoS), reduced RF transmit power, and reduced power consumption in cellular phones and other wireless devices.

Concepts[edit]

A phase-locked loop is an electronic component or system comprising a closed loop for controlling the phase of an oscillator while comparing it with the phase of an input or reference signal. An indirect frequency synthesizer uses a PLL. In an all-digital PLL, a voltage-controlled oscillator (VCO) is controlled using a digital, rather than analog, control signal. The phase detector gives a signal proportional to the phase difference between two signals; in a PLL, one signal is the reference, and the other is the output of the controlled oscillator (or a divider driven by the oscillator).

In a unibit phase-locked loop, the phase is measured using only one bit of the reference and output counters, the most significant bit (MSB). In a multibit phase-locked loop, the phase is measured using more than one bit of the reference and output counters, usually including the most significant bit.

The unibit PLL[edit]

In unibit PLLs, the output frequency is defined by the input frequency and the modulo count of the two counters. In each counter, only the most significant bit (MSB) is used. The other output lines of the counters are ignored; this is wasted information.

PLL structure and performance[edit]

A PLL includes a phase detector, filter and oscillator connected in a closed loop, so the oscillator frequency follows (equals) the input frequency. Although the average output frequency equals the input frequency, the oscillator's frequency fluctuates or vibrates about that average value. The closed loop operates to correct such frequency deviations; higher performance PLL reduces these fluctuations to lower values, however these deviations can never be stopped. See Control theory. Phase noise, spurious emission, and jitter are results of the above phenomena.

PLL synthesizer characteristics[edit]

  • PLL frequency synthesizers are widely used in modern telecommunications. For example, a cellular phone may include three to six PLLs.
  • The phase noise may interfere with other subscribers, to reduce their quality of service. The interference is mutual. If the noise is reduced, faster communications are possible, to increase the symbol rate using more complex modulation schemes - that is, transmitting more bits per sample.

Frequency settling time is the time it takes the PLL to hop to another frequency. Frequency hopping is used in GSM, and still more in modern systems. In CDMA, frequency hopping achieves better performance than phase coding.

Fine frequency resolution is the capability of a PLL to generate closely spaced frequencies. For example, a cellular network may require a mobile phone to set its frequency at any of a plurality of values, spaced 30 kHz or 10 kHz.

The performance envelope of a PLL defines the interrelation between the above essential criteria of performance - for example improving the frequency resolution will result in a slower PLL and higher phase noise, etc.

The PLL Multibit expands the performance envelope of the PLL - it enables to achieve faster settling time together with fine frequency resolution and with lower phase noise.

Effects of unibit[edit]

As one progresses from the MSB toward the least significant bit (LSB), the frequency increases. For a binary counter, each next bit is at twice the frequency of the previous one. For modulo counters, the relationship is more complicated.

Only the MSB of the two counters are at the same frequency. The other bits in one counter have different frequencies from those in the other counter.

All the bits at the output of one counter, together, represent a digital bus. Thus, in a PLL frequency synthesizer there are two buses, one for the reference counter, the other for the output (or VCO) counter. In a uni-bit PLL, of the two digital buses, only one bit (line) of each is used. All the rest of the information is lost.

Complexity of PLL design[edit]

PLL design is an interdisciplinary task, difficult even for experts in PLLs. This - for the Unibit PLL, which is simpler than the Multibit PLL. The design should take into account:[2][3][4][5][6][7]

  • [Control theory, closed loop system.
  • Radio frequency RF design - the oscillator, high frequency components
  • Analog circuits - loop filter
  • Digital circuits - counters, phase measurement
  • RFI/EMI, shielding, grounding
  • Statistics of noise and phase noise in electronic components and circuits.

The Multibit PLL[edit]

Principle of operation[edit]

The above PLL uses more of the bits in the two counters. There is a difficult problem, of comparing signals at different frequencies, in two digital buses which count to a different final value.

Improved performance is possible by using the faster bits of the counters, taking into account the additional available information.

The operation of the PLL is further disrupted by overflow in the counters. This effect is only relevant in multibit PLLs; for Unibit PLL, there is only the one-bit signal MSB, therefore no overflow is possible.

Implementation[edit]

The additional degree of freedom in Multibit PLLs allows to adapt each PLL to specific requirements. This can be effectively implemented with programmable logic devices (PLD), for example those manufactured by Altera Corp.[7] Altera provides both digital components and advanced design tools for using and programming the components.

Early multibit PLLs used a microprocessor, a microcontroller or DSP to close the loop in a smart implementation.[8][9][10][11][12][13][14]

Benefits[edit]

A multibit PLL offers fine frequency resolution and fast frequency hopping, together with lower phase noise and lower power consumption. It thus enhances the overall performance envelope of the PLL.

The loop bandwidth can be optimized for phase noise performance and/or frequency settling speed; it depends less on the frequency resolution.

Improving the PLL performance can make better use of the frequency spectrum and reduce transmit power. And indeed, PLL performance is being constantly improved.[1]

References[edit]

  1. ^ a b Marc Zuta, "A new PLL with fast settling time and low phase noise". Microwave Journal, June 1998, pp. 94–108.
  2. ^ Floyd M. Gardner, Phaselock Techniques, Second edition. ISBN 0-471-04294-3
  3. ^ Vadim Manassewitsch: Frequency Synthesizers, Theory and Design. Second edition. ISBN 0-471-07917-0
  4. ^ Bar-Giora Goldberg, Digital Techniques in Frequency Synthesis
  5. ^ William C. Lindsey, Marvin K. Simon, Telecommunication Systems Engineering
  6. ^ Marvin Frerking, Crystal Oscillator Design and Temperature Compensation
  7. ^ a b "Device Data Book". Altera Corporation. 
  8. ^ U.S. Patent No. 4450518 ITT Industries, Inc. A closed loop control system for adjusting an oscillator frequency using a microprocessor and DAC
  9. ^ U.S. Patent No. 4503401 Allied Corporation A PLL with a microprocessor controlling a VCO for extending the frequency range of the PLLO
  10. ^ U.S. Patent No. 4646030 Tektronix, Inc. Oscillator is frequency and phase locked. Uses microprocessor and DAC, DAC output to programmable delay circuit
  11. ^ U.S. Patent No. 5053723 U.S. Philips Corp. PLL with microprocessor controlling a VCO through a switching network and PDM
  12. ^ U.S. Patent No. 5182528 Zuta Marc, Computer controls oscillator through both a coarse digital bus and a fine analog control using a DAC
  13. ^ U.S. Patent No. 5363419 Advanced Micro Devices, Inc. VCO is controlled using analog signal derived from counter and DAC, and a coarse loop
  14. ^ U.S. Patent No. 5448763 Motorola Inc. PLL synthesizer, processor determines the channel spacing. PLL has faster lock time and lower noise