|Max. CPU clock rate||2.4 GHz to 4.25 GHz|
|Min. feature size||45 nm|
|Instruction set||Power Architecture (Power ISA v.2.06)|
|Cores||4, 6, 8|
|L1 cache||32+32 KB/core|
|L2 cache||256 KB/core|
|L3 cache||32 MB|
POWER7 is a Power Architecture based superscalar symmetric multiprocessor released in 2010 that succeeded the POWER6. POWER7 was developed by IBM at several sites including IBM's Rochester, MN; Austin, TX; Essex Junction, Vermont; T. J. Watson Research Center, NY; Bromont, QC and IBM Deutschland Research & Development GmbH, Böblingen, Germany laboratories. IBM announced servers based on POWER7 on 8 February 2010.
IBM won a $244 million DARPA contract in November 2006 to develop a petascale supercomputer architecture before the end of 2010 in the HPCS project. The contract also states that the architecture shall be available commercially. IBM's proposal, PERCS (Productive, Easy-to-use, Reliable Computer System), which won them the contract, is based on the POWER7 processor, AIX operating system and General Parallel File System.
One feature that IBM and DARPA collaborated on is modifying the addressing and page table hardware to support global shared memory space for POWER7 clusters. This enables research scientists to program a cluster as if it were a single system, without using message passing. From a productivity standpoint, this is essential since some scientists are not conversant with MPI or other parallel programming techniques used in clusters.
The POWER7 superscalar symmetric multiprocessor architecture was a substantial evolution from the POWER6 design, focusing more on power efficiency through multiple cores and simultaneous multithreading (SMT). The POWER6 architecture was built from the ground up for frequencies, at the cost of power efficiency and achieved a remarkable 5 GHz. IBM claimed at ISCA 29 that peak performance was achieved by high frequency designs with 10-20 FO4 delays per pipeline stage at the cost of power efficiency. However, the POWER6 binary floating-point unit achieves a “6-cycle, 13-FO4 pipeline”.
Therefore the pipeline for the POWER7 CPU has been changed again, just as it was for the POWER5 and POWER6 designs. In some respects, this rework is similar to Intel’s turn in 2005 that left the P4 7th-generation x86 microarchitecture. While the POWER6 features a dual-core processor, each capable of two-way simultaneous multithreading (SMT), the IBM POWER 7 processor has up to eight cores, and four threads per core, for a total capacity of 32 simultaneous threads.
The POWER7 superscalar symmetric multiprocessor is available with 4, 6, or 8 physical cores per microchip, in a 1 to 32-way design, with up to 1024 SMTs and a slightly different microarchitecture and interfaces for supporting extended/Sub-Specifications in reference to the Power ISA and/or different system architectures. For example in the Supercomputing (HPC) System Power 775 it is packaged as a 32-way quad-chip-module (QCM) with 256 physical cores and 1024 SMTs. There is also a special TurboCore mode that can turn off half of the cores from an eight-core processor, but those 4 cores have access to all the memory controllers and L3 cache at increased clock speeds. This makes each core's performance higher which is important for workloads which require the fastest sequential performance at the cost of reduced parallel performance. TurboCore mode can reduce "software costs in half for those applications that are licensed per core, while increasing per core performance from that software." The new IBM Power 780 scalable, high-end servers featuring the new TurboCore workload optimizing mode and delivering up to double performance per core of POWER6 based systems.
Each core is capable of four-way simultaneous multithreading (SMT). The POWER7 has approximately 1.2 billion transistors and is 567 mm2 large fabricated on a 45 nm process. A notable difference from POWER6 is that the POWER7 executes instructions out-of-order instead of in-order. Despite the decrease in maximum frequency compared to POWER6 (4.25 GHz vs 5.0 GHz), each core has higher performance than the POWER6, while having up to 4 times the number of cores.
- 45 nm SOI process, 567 mm2
- 1.2 billion transistors
- 3.0 – 4.25 GHz clock speed
- max 4 chips per quad-chip module
- 4, 6 or 8 C1 cores per chip
- 32+32 kB L1 instruction and data cache (per core)
- 256 kB L2 Cache (per C1 core)
- 4 MB L3 cache per C1 core with maximum up to 32MB supported. The cache is implemented in eDRAM, which does not require as many transistors per cell as a standard SRAM so it allows for a larger cache while using the same area as SRAM.
"Each POWER7 processor core implements aggressive out-of-order (OoO) instruction execution to drive high efficiency in the use of available execution paths. The POWER7 processor has an Instruction Sequence Unit that is capable of dispatching up to six instructions per cycle to a set of queues. Up to eight instructions per cycle can be issued to the Instruction Execution units. The POWER7 processor has a set of twelve execution units as [described above]"
This gives the following theoretical performance figures (based on a 4.14 GHz 8 core implementation):
- max 99.36 GFLOPS per core
- max 794.88 GFLOPS per chip
4 64-bit SIMD units per core, and a 128-bit SIMD VMX unit per core, can do 12 Multiply-Adds per cycle, giving 24 FP ops per cycle. At 4.14 GHz, that gives 4.14 billion * 24 = 99.36 GFLOPS, and at 8 cores, 794.88 GFLOPS.
IBM introduced the POWER7+ processor at the Hot Chips 24 conference in August 2012. It is an updated version with higher speeds, more cache and integrated accelerators. It is manufactured on a 32 nm fabrication process.
The first boxes to ship with the POWER7+ processors were IBM POWER 770 and 780 servers. The chips have up to 80 MB of L3 cache (10 MB/core), improved clock speeds (up to 4.4 GHz) and 20 LPARs per core.
As of October 2011, the range of POWER7 systems includes "Express" models (710, 720, 730, 740 and 750), Enterprise models (770, 780 and 795) and High Performance computing models (755 and 775). Enterprise models differ in having Capacity on Demand capabilities. Maximum specifications are shown in the table below.
|Name||Number of sockets||Number of cores||CPU clock frequency|
|710 Express||1||6||4.2 GHz|
|710 Express||1||8||4.2 GHz|
|720 Express||1||8||3.6 GHz|
|730 Express||2||12||4.2 GHz|
|730 Express||2||16||3.6 GHz or 4.2 GHz|
|740 Express||2||12||4.2 GHz|
|740 Express||2||16||3.6 GHz or 4.2 GHz|
|750 Express||4||24||3.72 GHz|
|750 Express||4||32||3.22 GHz or 3.61 GHz|
|775 (Per Node)||32||256||3.83 GHz|
|780 (MaxCore mode)||8||64||3.92 GHz|
|780 (TurboCore mode)||8||32||4.14 GHz|
|780 (4 Socket Node)||16||96||3.44 GHz|
|795 (MaxCore mode)||32||256||4.0 GHz|
|795 (TurboCore mode)||32||128||4.25 GHz|
|Name||Number of cores||CPU clock frequency||Blade slots required|
|BladeCenter PS700||4||3.0 GHz||1|
|BladeCenter PS701||8||3.0 GHz||1|
|BladeCenter PS702||16||3.0 GHz||2|
|BladeCenter PS703||16||2.4 GHz||1|
|BladeCenter PS704||32||2.4 GHz||2|
The following are supercomputer projects that use the POWER7 processor
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