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PSoC (Programmable System-on-Chip) is a family of integrated circuits made by Cypress Semiconductor. These chips include a CPU and mixed-signal arrays of configurable integrated analog and digital peripherals.
Commercial PSoC shipments began in 2002.
Cypress released the fourth generation, PSoC 4, in April 2013. The PSoC 4 features a 32-bit ARM Cortex-M0 CPU, with programmable analog blocks (OpAmps, Comparators), programmable digital blocks (PLD-based UDBs), programmable routing and flexible GPIO (route any function to any pin), a Serial Communication Block (for SPI, UART, I2C), a Timer/Counter/PWM block and more. 
PSoC is used in devices as simple as Sonicare toothbrushes and Adidas sneakers, and as complex as the TiVo set-top box. One PSoC, using CapSense, controls the touch-sensitive scroll wheel on the Apple iPod click wheel
A PSoC integrated circuit is composed of a core, configurable analog and digital blocks, and programmable routing and interconnect. The configurable blocks in a PSoC are the biggest difference from other microcontrollers.
Configurable analog and digital blocks
Using configurable analog and digital blocks, designers can create and change mixed-signal embedded applications. The digital blocks are state machines that are configured using the blocks registers. There are two types of digital blocks, Digital Building Blocks (DBBxx) and Digital Communication Blocks (DCBxx). Only the communication blocks can contain serial I/O user modules, such as SPI, UART, etc.
Each digital block is considered an 8-bit resources that designers can configure using pre-built digital functions or user modules (UM), or, by combining blocks, turn them into 16-, 24-, or 32-bit resources. Concatenating UMs together is how 16-bit PWMs and timers are created.
There are two types of analog blocks. The continuous time (CT) blocks are composed of an op-amp circuit and designated as ACBxx where xx is 00-03. The other type is the switch cap (SC) blocks, which allow complex analog signal flows and are designated by ASCxy where x is the row and y is the column of the analog block. Designers can modify and personalize each module to any design.
Programmable routing and interconnect
PSoC mixed-signal arrays' flexible routing allows designers to route signals to and from I/O pins more freely than with many competing microcontrollers. Global buses allow for signal multiplexing and for performing logic operations. Cypress suggests that this allows designers to configure a design and make improvements more easily and faster and with fewer PCB redesigns than a digital logic gate approach or competing microcontrollers with more fixed function pins.
PSoC is a software configured, mixed-signal array with a built-in MCU core. There are three different families of devices (2012):
- CY8C2xxxx series - Named 'PSoC 1' with CPU M8C
- CY8C3xxxx series - Named 'PSoC 3' with CPU 8051
- CY8C4xxxx series - Named 'PSoC 4' with CPU ARM Cortex M0
- CY8C5xxxx series - Named 'PSoC 5' with CPU ARM Cortex M3
PSoC has three separate memory spaces: paged SRAM for data, Flash memory for instructions and fixed data, and I/O Registers for controlling and accessing the configurable logic blocks and functions. The device is created using SONOS technology.
PSoC resembles an ASIC: blocks can be assigned a wide range of functions and interconnected on-chip. Unlike an ASIC, there is no special manufacturing process required to create the custom configuration - only startup code that is created by Cypress' PSoC Designer for PSoC 1 or PSoC Creator for PSoC 3, PSoC 4 and PSoC 5 IDE.
PSoC resembles an FPGA in that at power up it must be configured, but this configuration occurs by loading instructions from the built-in Flash memory.
PSoC most closely resembles a microcontroller combined with a PLD and programmable analog. Code is executed to interact with the user-specified peripheral functions (called "Components"), using automatically generated APIs and interrupt routines. PSoC Designer for PSoC 1 and PSoC Creator for PSoC 3, PSoC 4 and PSoC 5 generate the startup configuration code. Both integrate APIs that initialize the user selected components upon the users needs in a Visual-Studio-like GUI.
|PSoC 1||PSoC 3||PSoC 4||PSoC 5||PSoC Tools|
|Performance optimized 8-bit M8C core||Performance optimized single cycle 8-bit 8051 core||High-performance 32-bit ARM Cortex-M0||High-performance 32-bit ARM Cortex-M3||PSoC Creator
Drag-n-drop based free IDE for PSoC 3, PSoC 4 and PSoC 5
|Up to 24 MHz, 4 MIPS
Flash 4 KB to 32 KB
SRAM 256 bytes to 2 KB
Operation 1.7 V to 5.25 V
|Up to 67 MHz, 33 MIPS
Flash 8 KB to 64 KB
SRAM 3 KB to 8 KB
Operation 0.5 V to 5.5 V
|Up to 48 MHz, MIPS
Flash 16 KB to 32 KB
SRAM 4 KB
Operation 1.71 V to 5.5 V
|Up to 67 MHz, 84 MIPS
Flash 32 KB to 256 KB
SRAM 16 KB to 64 KB
Operation 2.7 V to 5.5 V
Drag-n-drop based free IDE for PSoC 1
|1 Delta-Sigma ADC (6 to 14-bit)
131 ksps @ 8-bit
Voltage Precision ±1.53%
Up to two DACs (6 to 8-bit)
|1 Delta-Sigma ADC (8 to 20-bit)
192 ksps @ 12-bit
Voltage Precision ±0.1%
Up to four DACs (8-bit)
|1 SAR ADC (12-bit) ;1 Msps @ 12-bit
Up to 2 DACs (8-bit)
|1 Delta-Sigma ADC (8 to 20-bit); 2 SAR ADCs (12-bit)
192 ksps @12-bit;1 Msps @ 12-bit
Voltage Precision ±1.0%
Up to four DACs (8-bit)
|PSoC 3 Featured Kits
CY8CKIT-001 Development Kit
CY8CKIT-030 Development Kit
|Active: 2 mA, Sleep: 3 μA
FS USB 2.0, I²C, SPI, UART
|Active: 1.2 mA, Sleep: 1 μA, Hibernate: 200 nA
FS USB 2.0, I²C, SPI, UART, CAN, LIN, I²S
|Active: 1.6 mA, Sleep: 1.3 μA, Hibernate: 150 nA
I²C, SPI, UART
|Active: 2 mA, Sleep: 2 μA, Hibernate: 300 nA
FS USB 2.0, I²C, SPI, UART, LIN, I²S
|PSoC 5 Featured Kits
CY8CKIT-001 Development Kit
CY8CKIT-050 Development Kit
|Requires ICE Cube and FlexPods||On-chip JTAG, Debug and Trace; SWD, SWV||On-chip JTAG, Debug and Trace; SWD, SWV||On-chip JTAG, Debug and Trace; SWD, SWV||PSoC 1 Featured Kits
CY8CKIT-001 Development Kit
|Up to 64 I/O||Up to 72 I/O||Up to 36 I/O||Up to 72 I/O||PSoC 4 Featured Kits
CY8CKIT-042 Pioneer Kit
- PSoc Kit
- FPGA Configuration via the PSoC(R) Programmable System-on-Chip
- (4) CapSense buttons
- I²C temperature sensor
- (2) 6-pin expansion header
- USB-to-UART bridge interface
- I²C port
- SPI and BPI configuration
- Xilinx JTAG interface
- PSoC Designer
This is the first generation software IDE to design and debug and program the PSoC 1 devices. It introduced unique features including a library of pre-characterized analog and digital peripherals in a drag-and-drop design environment which could then be customized to specific design needs by leveraging the dynamically generated API libraries of code.
- PSoC Creator
PSoC Creator is the second generation software IDE to design debug and program the PSoC 3 and PSoC 5 devices. The development IDE is combined with an easy to use graphical design editor to form a powerful hardware/software co-design environment. PSoC Creator consists of two basic building blocks. The program that allows the user to select, configure and connect existing circuits on the chip and the components which are the equivalent of peripherals on MCUs. What makes PSoC intriguing is the possibility to create own application specific peripherals in hardware. On top of that, Cypress publishes component packs several times a year. Basically PSoC users get new peripherals for their existing hardware without being charged or having to buy new hardware. PSoC Creator also lets users connect any peripheral to any pin (except supply pins).
The amount of documentation for all ARM chips is daunting, especially for newcomers. The documentation for microcontrollers from past decades would easily be inclusive in a single document, but as chips have evolved so has the documentation grown. The total documentation is especially hard to grasp for all ARM chips since it consists of documents from the IC manufacturer (Cypress Semiconductor) and documents from CPU core vendor (ARM Holdings).
A typical top-down documentation tree is: manufacturer website, manufacturer marketing slides, manufacturer datasheet for the exact physical chip, manufacturer detailed reference manual that describes common peripherals and aspects of a physical chip family, ARM core generic user guide, ARM core technical reference manual, ARM architecture reference manual that describes the instruction set(s).
- PSoC documentation tree (top to bottom)
- PSoC website.
- PSoC marketing slides.
- PSoC datasheet.
- PSoC reference manuals.
- ARM core website.
- ARM core generic user guide.
- ARM core technical reference manual.
- ARM architecture reference manual.
Cypress Semiconductor has additional documents, such as: evaluation board user manuals, application notes, getting started guides, software library documents, errata, and more. See External Links section for links to official PSoC and ARM documents.
- ARM architecture, List of ARM microprocessor cores, ARM Cortex-M
- Microcontroller, List of common microcontrollers
- Embedded system, Single-board microcontroller
- Interrupt, Interrupt handler, List of real-time operating systems
- JTAG, SWD
- Field-programmable analog array, Reconfigurable computing
- ARM Cortex-M
- Digital Signal Processing and Applications Using the ARM Cortex M4; 1st Edition; Donald Reay; Wiley; 250 pages; 2014; ISBN 978-1118859049.
- Assembly Language Programming : ARM Cortex-M3; 1st Edition; Vincent Mahout; Wiley-ISTE; 256 pages; 2012; ISBN 978-1848213296.
- The Definitive Guide to the ARM Cortex-M3 and Cortex-M4 Processors; 3rd Edition; Joseph Yiu; Newnes; 600 pages; 2013; ISBN 978-0124080829.
- The Definitive Guide to the ARM Cortex-M0; 1st Edition; Joseph Yiu; Newnes; 552 pages; 2011; ISBN 978-0-12-385477-3.
|Wikibooks has a book on the topic of: Embedded Systems/Cypress PSoC Microcontroller|
- STM32 Official Documents
- ARM Official Documents