Pipelining (DSP implementation)

From Wikipedia, the free encyclopedia
Jump to: navigation, search

Pipelining is an important technique used in several applications such as digital signal processing (DSP) systems, microprocessors, etc. It originates from the idea of a water pipe with continuous water sent in without waiting for the water in the pipe to come out. Accordingly, it results in speed enhancement for the critical path in most DSP systems. For example, it can either increase the clock speed or reduce the power consumption at the same speed in a DSP system.

Concept[edit]

Conceptually, pipelining puts different function units working in parallel. In computer architectures, it usually represents an implementation technique allowing multiple instructions are overlapped in execution to be parallel. Consider an informal example in the following figure. A function includes three sub-function units (F0, F1 and F2). Assume that there are three tasks (T0, T1 and T2) being operated by these three function units and they can be operated independently. The time for each function unit to complete a task is the same and will occupy a slot in the schedule.
In such condition, if we put these three units and tasks in a sequential order, the required time to complete them is five slots.

Non-pipelined.png

However, if we pipeline T0 to T2 in parallel, the aggregate time is reduced to three slots, which is smaller than in a sequential order.

Pipelined structure function units.png

Therefore, it is possible for an adequate pipelined design to achieve significant enhancement on speed.

Costs and disadvantages[edit]

Pipelining does not decrease the processing time for a single task. Instead, we still need to cost the same runtime efforts on the same task when compared to a full sequential design. Please note that the advantage of pipelining is that it increases the throughput of the system when processing a stream of task.

Nevertheless, applying too many pipelined functions usually leads to the increase of latency. The time required for a task to propagate through a full pipe prolongs. Further a pipelined system typically requires more resources and costs (buffers, circuits, processing units, memory etc.) to perform parallel working since the reuse of resources across different stages is restricted.

Comparison with parallel approaches[edit]

The other technique to enhance the efficiency of designs is called parallel techniques, which usually confuses with pipelining techniques. The core difference is that parallel techniques usually duplicate function units and distribute all the input tasks into different function units. Therefore, it can complete more tasks per unit time but suffers expensive resource costs.

For the previous example, the parallel technique duplicate each function units into another two. Accordingly, all the tasks can be operated under duplicated function units with the same function simultaneously. The time to complete these three tasks is reduced to three slots.

Pipelining in FIR filters[edit]

Consider a 3-tap FIR filter:[1]

y(n)=ax(n)+bx(n-1)+cx(n-2)

which is as shown in the following figure.

Assume the calculation time for multiplication units is Tm and Ta for add units. The critical path, representing the minimum time required for processing a new sample, is limited by 1 multiplication and 2 add function units. Therefore, the sample period is given by

{T_{sample} \ge T_m + 2T_a }

Pipelined FIR filters.png

However, such structure may not be suitable for the design with the requirement of high speed. To reduce the sampling period, we can introduce extra pipelining registers along the critical data path. Then the structure is partitioned into two stages and the data produced in the first stage will be stored in the introduced registers, delaying one clock to the second stage. The data in first three clocks is recorded in the following table. Under such pipelined structure, the sample period is reduced to

T_{sample} \ge T_m + T_a .

Pipelined FIR filters2.png


Pipelined FIR filters table.png

Pipelining in 1st-Order IIR filters[edit]

By combining look-ahead techniques and pipelining,[2] we are able to enhance the sample rate of target design. Look-ahead pipelining will add canceling poles and zeroes to the transfer function such that the coefficients of the following terms in the denominator of the transfer function are zero.
 \{z^{-1},...,z^{-(M-1)}\}

Then, the output sample y(n) can be computed in terms of the inputs and the output sample y(n-M) such that there are M delay elements in the critical loop. These elements are then used to pipeline the critical loop by M stages so that the sample rate can be increased by a factor M.


Consider the 1st-order IIR filter transfer function
H(z)=\frac{1}{1-a*z^{-1}}

The output y(n) can be computed in terms of the input u(n) and the previous output.
y(n) = a*y(n-1) + u(n)

In a straightforward structure to design such function, the sample rate of this recursive filter is restricted by the calculation time of one multiply-add operation.

To pipeline such design, we observe that H has a pole at
z=a, a\le1

Therefore, in a 3-stage pipelined equivalent stable filter, the transfer function can be derived by adding poles and zeros at
z=ae^{\pm(\frac{2j\pi}{3})}

and is given by
 H(z)=\frac{1+a*z^{-1}+a^{2}*z^{-2}}{1-a^{3}*z^{-3}}

Therefore, the corresponding sample rate can be increased by a factor 3.

Other Pipelined DSP systems[edit]

  • Pipelined Walsh–Fourier transform[3]
  • Pipelined unitary transforms[4]
  • Pipelined DFT[5]
  • Pipelined FFT[6]
  • etc.

References[edit]

  1. ^ K.K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, John Wiley, 1999
  2. ^ Slides for VLSI Digital Signal Processing Systems: Design and Implementation John Wiley & Sons, 1999 (ISBN Number: 0-471-24186-5): http://www.ece.umn.edu/users/parhi/slides.html
  3. ^ M. R. Ashouri and Anthony G. Constantinides, "A pipeline fast Walsh Fourier transform," in Proc. IEEE Int. Conf. ASSP Hartford, CT, May 9–11), pp. 515-518, 1977.
  4. ^ Fino, B.J.; Algazi, V.R.; , "Parallel and pipeline computation of fast unitary transforms," Electronics Letters , vol.11, no.5, pp.93-94, March 6, 1975
  5. ^ Tzou, K.-H.; Morgan, N.P.; , "A fast pipelined DFT processor and its programming consideration," Electronic Circuits and Systems, IEE Proceedings G , vol.132, no.6, pp.273-276, December 1985
  6. ^ H. L. Gorginsky and G. A. Works, "A pipeline fast Fourier transform," IEEE Trans. Comput., vol. C-19, pp. 1015-1019, Nov. 1970.