Process variation (semiconductor)
Process variation is the naturally occurring variation in the attributes of transistors (length, widths, oxide thickness) when integrated circuits are fabricated. It becomes particularly important at smaller process nodes (<65 nm) as the variation becomes a larger percentage of the full length or width of the device and as feature sizes approach the fundamental dimensions such as the size of atoms and the wavelength of usable light for patterning lithography masks.
Process variation causes measurable and predictable variance in the output performance of all circuits but particularly analog circuits due to mismatch. If the variance causes the measured or simulated performance of a particular output metric (bandwidth, gain, rise time, etc.) to fall below or rise above the specification for the particular circuit or device it reduces the overall yield for that set of devices.
An analysis of systematic variation was performed by Schemmert and Zimmer in 1974 with their paper on threshold-voltage sensitivity. This research looked into the effect that the oxide thickness and implantation energy had on the threshold voltage of MOS devices.
sources of variations 1) gate oxide thickness 2) random dopant fluctuations 3) Device Geometry, Lithography in nanometer region
Semiconductor foundries run analyses on the variability of attributes of transistors (length, width, oxide thickness, etc.) for each new process node. These measurements are recorded and provided to customers such as fabless semiconductor companies. This set of files are generally referred to as "model files" in the industry and are used by EDA tools for simulation of designs.
Workarounds & Solutions
Designers using this approach run from tens to thousands of simulations to analyze how the outputs of the circuit will behave according to the measured variability of the transistors for that particular process. The measured criteria for transistors are recorded in model files given to designers for simulating their circuits before simulation.
The most basic approach is for designers to increase the size of devices which are sensitive to mismatch.
This is used to reduce variation due to polishing, etc.
To reduce roughness of line edges, advanced lithography techniques are used.
- Patrick Drennan, "Understanding MOSFET Mismatch for Analog Design" IEEE Journal of Solid-State Circuits, Vol 38, No 3, March 2003 http://www.solidodesign.com/uploads/drennan-mismatch.pdf
- W. Shockley, “Problems related to p-n junctions in silicon.” Solid-State Electronics, Volume 2, January 1961, pp. 35–67.
- W. Schemmert, G. Zimmer, "Threshold-voltage sensitivity of ion-implanted m.o.s.transistors due to process variations." Electronics Letters, Volume 10, Issue 9, May 2, 1974, pp. 151-152
- "Managing Process Variation in Intel's 45nm CMOS Technology." Intel Technology Journal, Volume 12, Issue 2 June 17, 2008 http://www.intel.com/technology/itj/2008/v12i2/3-managing/1-abstract.htm