|L1 cache||192 KiB (128 KiB I-cache with parity, 64 KiB D-cache with ECC) per core|
|L2 cache||2 MiB|
Project Denver is the codename of a microarchitecture that emulates the ARMv8-A 64-bit instruction set designed by Nvidia using a combination of simple hardware decoder and software-based dynamic recompilation. Denver is a very wide in-order superscalar pipeline. Its design makes it suitable for integration with other SIPs cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).
- Pipelined processor with 7-way superscalar execution pipeline
- 128 KiB instruction + 64 KiB data L1 cache per core (both 4-way), 2 MiB L2 cache (16-way shared)
- Denver also sets aside 128 MiB of main memory as an interpretation cache, that the main operating system won’t be able to see or access.
- Running at up to 2.5 GHz
- ARM code is translated either by a hardware translator or through software emulation to an instruction set that is internal to Project Denver. ARM instructions can be reordered, removed if they do not contribute to the end result, or otherwise optimized if software emulation is used.
The existence of Project Denver was revealed at the 2011 Consumer Electronics Show. In a March 4, 2011 Q&A article CEO Jen-Hsun Huang revealed that Project Denver is a five year 64-bit ARMv8-A architecture CPU development on which hundreds of engineers had already worked for three and half years and which also has 32-bit ARM instruction set (ARMv7) backward compatibility. Project Denver was started in Stexar company (Colorado) as an x86-compatible processor using binary translation like in Transmeta's projects. Stexar was acquired by Nvidia in 2006.
According to Tom's Hardware, there are engineers from Intel, AMD, HP, Sun and Transmeta on the Denver team, and they have extensive experience in designing superscalar CPUs with out-of-order execution, very long instruction words (VLIW) and simultaneous multithreading (SMT).
According to Charlie Demerjian, the Project Denver CPU may internally translate the ARM instructions to an internal instruction set, using firmware in the CPU. Also according to Demerjian, Project Denver was originally intended to support both ARM and x86 code using code morphing technology from Transmeta, but was changed to the ARMv8-A 64-bit instruction set because Nvidia could not obtain a license to Intel's patents.
- Wasson, Scott (August 11, 2014). "Nvidia claims Haswell-class performance for Denver CPU core". The Tech Report. Retrieved August 14, 2014.
- Dally, Bill (January 5, 2011). ""PROJECT DENVER" PROCESSOR TO USHER IN NEW ERA OF COMPUTING". Official Nvidia blog.
- Template:Cite ref
- Anthony, Sebastian (January 6, 2014). "Tegra K1 64-bit Denver core analysis: Are Nvidia’s x86 efforts hidden within?". ExtremeTech. Retrieved January 7, 2014.
- Shimpi, Anand (January 5, 2014). "NVIDIA Announces Tegra K1 SoC with Optional Denver CPU Cores". Anandtech. Retrieved January 6, 2014.
- Shilov, Anton (January 19, 2011). "Nvidia Maxwell Graphics Processors to Have Integrated ARM General-Purpose Cores.". Xbit. Retrieved October 19, 2013.
- http://www.nvidia.com/object/ces2011.html Nvidia's press conference webcast
- Takahashi, Dean (March 4, 2011). "Q&A: Nvidia chief explains his strategy for winning in mobile computing".
- Valich, Theo (December 12, 2011). "NVIDIA Project Denver “Lost in Rockies”, to Debut in 2014-15".
- Miller, Paul (October 19, 2006). "NVIDIA has x86 CPU in the works?". Engadget. Retrieved October 19, 2013.
- Valich, Theo (March 20, 2013). "New Tegra Roadmap Reveals Logan, Parker and Kayla CUDA Strategy".
- Parrish, Kevin (October 14, 2013). "64-bit Nvidia Tegra 6 "Parker" Chip May Arrive in 2014. Devices with a 64-bit Tegra 6 could launch before the end of 2014.". Tom's Hardware & ExtremeTech. Retrieved October 19, 2013.
- Demerjian, Charlie (August 5, 2011). "What is Project Denver based on?". Semiaccurate.
- Valich, Theo (September 20, 2012). "NVIDIA Project Boulder Revealed: Tegra's Competitor Hides in GPU Group".