Q-Bus

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Q-Bus
Q-Bus
Created by Digital Equipment Corporation

The Q-bus[1] (also known as the LSI-11 Bus) was one of several bus technologies used with PDP and MicroVAX computer systems manufactured by the Digital Equipment Corporation of Maynard, Massachusetts.

The Q-bus was a less expensive version of Unibus using multiplexing so that address and data signals shared the same wires. This allowed both a physically smaller and less-expensive implementation of essentially the same functionality.

Over time, the physical address range of the Q-bus was expanded from 16 to 18 and then 22 bits. Block transfer modes were also added to the Q-bus.

Main features of the Q-bus[edit]

LSI-11/23 Q-Bus cards and slots
DEC BA213 cabinet; 12 Q-Bus-22 slots

Like the Unibus before it, the Q-bus used:

Memory-mapped I/O means that data cycles between any two devices, whether CPU, memory, or I/O devices, used the same protocols. On the Unibus, a range of physical addresses were dedicated for I/O devices. The Q-bus simplified this design by providing a specific signal (originally called BBS7, Bus Bank Select 7 but later generalized to be called BBSIO, Bus Bank Select I/O) that selected the range of addresses used by the I/O devices.

Byte addressing means that the physical address passed on the Unibus was interpreted as the address of a byte-sized quantity of data. Because the bus actually contained a data path that was two bytes wide, address bit [0] was subject to special interpretation and data on the bus had to travel in the correct byte lanes.

A strict Master-Slave relationship means that at any point in time, only one device could be the Master of the Q-bus. This master device could initiate data transactions which could then be responded to by a maximum of one selected slave device. (This had no effect on whether a given bus cycle was reading or writing data; the bus master could command either type of transaction.) At the end of the bus cycle, a bus arbitration protocol would then select the next device to be given mastership of the bus.

Asynchronous signaling means that the bus had no fixed cycle time; the duration of any particular data transfer cycle on the bus was determined solely by the master and slave devices participating in the current data cycle. These devices used handshake signals to control the timing of the data cycle. Timeout logic within the master device limited the maximum allowed length of any given bus cycle.

Depending on its generation, the Q-bus contained 16, 18, or 22 BDAL (Bus Data/Address Line) lines. 16, 18, or 22 BDAL lines were used for the physical address portion of each bus cycle. Eight or 16 DBAL lines were then re-used for the data portion(s) of each bus cycle. Newer generations of the bus allowed block mode transfer where a single bus address could be followed by more than one data cycle (with the transfers taking place at consecutive bus addresses). Because the address portion of each bus cycle can not transfer data, the use of block mode meant fewer address cycles and more time for data cycles, allowing increased bus data transfer bandwidth.

Bus mastery was awarded based on an I/O card's geographical proximity to the bus arbitrator (at the logical front of the bus); closer cards were granted priority over further cards.

Interrupts could be delivered to the Interrupt Fielding Processor at any of four priority levels. Within a given level, the cards closer to the IFP (at the front of the bus) took priority over cards further back on the bus. Interrupts were vectored: a card requesting an interrupt had its interrupt vector read by the IFP. In this way, the interrupts from all I/O cards in the system could be distinguished with no ambiguity.

Logic minimization[edit]

As with the Unibus, the signaling was carefully optimized so that the minimum amount of logic was required across the entire bus system. Asynchronous signaling was used but all responsibility for de-skewing of addresses and data was the responsibility of the current bus master, minimizing the complexity of the bus slave devices. The responsibility for timing-out failed bus cycles also was placed in the master devices. Similarly, the complexities of handling interrupt transactions were concentrated into the single Interrupt-Fielding Processor (the PDP-11 or VAX-11 computer) in the system.

Compatibility[edit]

The design of the Q-bus was very closely related to the design of the Unibus both in spirit and in detailed implementation. Adapters were available from Digital and from third parties that allowed Q-bus devices to be connected to Unibus-based computers and vice-versa. A number of I/O devices were available in either Unibus or Q-bus flavors; some of these devices had minor differences while many others were essentially identical.

Soviet clones[edit]

In Soviet systems (see 1801 series CPU), the Q-Bus architecture was called МПИ (Магистральный Параллельный Интерфейс, or parallel bus interface). Its main difference was that it supported up to four processors on the same bus. Otherwise it was completely binary and electrically compatible with the standard Q-Bus, except for the physical layout of connectors.

Cycle Types[edit]

The Q-Bus supports 6 basic transaction types

DATI Data in - master read - note no DATIB (not required)
DATO Data out - master write
DATOB Data out (byte)
DATIO Data in/out
DATIOB Data in/out (byte)
IAK Interrupt Acknowledge

Interfaces[edit]

A wide range of interface cards were available for the Q-Bus[2]

Part Number Part Name Form factor Function
A012 ADV11-A 16-channel 12-bit A/D
A020 16-channel A/D, relay switched
A026 AXV11-C 16-channel 12-bit A/D plus 2-channel 12-bit D/A
A6001 AAV11-A 4-channel 12-bit D/A
A6006 AAV11-C Digital-to-analogue converter
A8000 ADV11-C 16-channel 12-bit A/D
G7272 Grant continuity card
H223 MMV11-A 4-Kword 16-bit stack & drive assembly
H9270 4x4 Q-bus backplane
H9273-A 9x4 Q-bus backplane in AB only
H9276-A 9x4 Q-bus backplane, Q-22
H9281-BA Q 4x2 Q-bus backplane
H9281-BB Q 8x2 Q-bus backplane
L4002 VAX 4000-500 CPU card
M3104 DHV11-A 8-line async DMA MUX
M3106 DZQ11-M 4-line double-buffered async EIA MUX, with
M3106-PA DZQ11-M 4-line double-buffered async MUX with S-box
M3107 DHQ11-M 8-line async MUX module, DMA, Q-22
M3108-A DSV11-A 2-line sync SLU for BA23/123 (-AA is first unit,
M3108-P DSV11-S 2-line sync SLU for BA223 (-SF is first unit, -SG
M3121 DFA01-AA Dual integral modem, S-box, DF224 compatible
M3125 BITBUS to Q-bus interface
M3125-PA Q-22 bus interface to Intel BITBUS
M3125-YA Q-22 bus interface to Intel BITBUS, no handle
M3126 DFA01-BA Dual integral modem, Q-bus, S-box, UK version
M3127-PA DESQA-SA/SF Ethernet/thinwire S-box adaptor (DELQA+DESTA)
M3127-PB DESQA-SA/SF M3127-PA with handle access thinwire pushbutton
M3128 QBIC Q-bus interface to VMI CCIC
M3129 KMV11 NRZI/RS422 data converter for KMV11
M4002 KWV11-C Programmable realtime clock
M5010 32-bit non-isolated dc input module
M5011 16-bit non-isolated dc input module
M5012 16-bit isolated dc input module
M5012-YA 16-bit isolated dc input module (TTL compatible)
M5013 8-bit isolated ac input module
M5014 Dual input counter, 16-bit
M5016 Quad input counter/prescalar, 8-bit
M5031 16-channel isolated dc interrupt module, 16-bit
M5976-AA Q-bus to SCSI adaptor for BA23/BA123 enclosures
M5976-SA Q-bus to SCSI adaptor for BA200/BA400 enclosures
M5977-AA SCSI to Q-bus controller (MSCP/TMSCP) for 11/83
M6010 32-bit non-isolated dc output module
M6010-YA 32-bit non-isolated dc output module (TTL
M6011 Non-isolated dc one-shot output module
M6012 8-bit isolated dc output module
M6013 8-bit isolated ac output module
M6014 Dual 16-bit output converter
M6015 16-bit retentive dc output module
M7061 VSV11-F Raster graphics sync generator & cursor control
M7062 VSV11-MA Raster graphics image memory
M7064 VSV11 Raster graphics image processor card
M7066 VTV01 Video Display Sys: UNIBUS to Q-bus converter
M7135 KD32-AA microVAX I datapath with G floating point
M7135-YA KD32-AB microVAX I datapath with D floating point
M7136 KD32-AA/AB microVAX I memory control
M7142 VK170-CA Serial video module, CRT control logic,
M7164 KDA50-Q Q-bus SDI disk adaptor, Q-22 (1 of 2)
M7165 KDA50-Q Q-bus SDI disk adaptor, Q-22 (2 of 2)
M7168 VCB02 4-plane colour bitmap module
M7169 VCB02 4-plane video controller module
M7193 DRQ11-CA DMA interface, 16-bit
M7195-FA MXV11-BF 128-Kbyte RAM, 2 async EIA SLU, I/O, clock,
M7196 TSV05 TSV05 controller for Q/Q22 bus
M7264 KD11-F 11/03 processor with 4-Kword MOS RAM
M7264-AA KD11-F 11/03 processor with 4-Kword MOS RAM
M7264-AB KD11-F 11/03 processor with 4-Kword MOS RAM
M7264-BB KD11-F 11/03 processor with 4-Kword MOS RAM & DIBOL microm
M7264-CB KD11-F 11/03 processor with 4-Kword MOS RAM
M7264-DB KD11-F 11/03 processor with 4-Kword MOS RAM
M7264-EB KD11-F 11/03 processor with 4-Kword MOS RAM
M7264-FB KD11-F 11/03 processor with 4-Kword MOS RAM
M7264-HB KD11-F 11/03 processor with 4-Kword MOS RAM
M7264-JB KD11-F 11/03 processor with 4-Kword MOS RAM
M7264-YA KD11-H 11/03 processor with 0-Kword RAM
M7264-YB KD11-Q 11/03 processor with 0-Kword RAM & DIBOL microm
M7264-YC KD11-H 11/03 processor with 0-Kword RAM
M7268 RKV11 RK11-D to Q-bus adaptor
M7269 RKV11 RK05 controller
M727 KA11 11/20 State control module
M727-YA M727 for KH11-A
M7270 KD11-HA LSI-11/2 CPU, 16-bit
M7458-AA MSV11-RA 1-Mbyte PMI/Q22 parity memory with CSR
M7500 KMV1A-S Programmable comms controller, BA2xxx.
M7502 Single-line high speed intelligent communication
M7504 DEQNA-AA Q-bus (Q-22) to ethernet adaptor, obsolete for VMS 5.x and above (use DELQA)
M7506-AA MSV11-MA 512-Kbyte 18-bit RAM
M7506-AT MSV11-MA 512-kbyte 22-bit parity/CSR MOS RAM
M7506-BA MSV11-MB 1-Mbyte RAM
M7506-BC MSV11-MB 1-Mbyte RAM
M7506-BE MSV11-MB 1-Mbyte 22-bit parity/CSR MOS RAM
M7506-BF MSV11-MB 1-Mbyte RAM
M7506-BH MSV11-MB 1-Mbyte RAM
M7506-BP MSV11-MB 1-Mbyte RAM
M7506-BT MSV11-MB 1-Mbyte 22-bit parity/CSR MOS RAM
M7506-BU MSV11-MB 1-Mbyte 22-bit parity/CSR MOS RAM
M7506-BV MSV11-MB 1-Mbyte 22-bit parity/CSR MOS RAM
M7512 RQDX1E RQDX extender for RQDX1; must be the last item in the backplane, below the RQDX1
M7513 RQDXE RQDX extender for RQDX2/3 (-AA for BA23, -FA for
M7516 DELQA-M Ethernet interface (replaces DEQNA)
M7516-PA DELQA Q-22 high-performance ethernet adaptor
M7546 TQK50-AA TMSCP controller for TK50 tape unit
M7551-AA MSV11-QA 1-Mbyte 22-bit parity/CSR MOS RAM
M7551-BA MSV11-QB 2-Mbyte 22-bit parity/CSR MOS RAM
M7551-CA MSV11-QC 4-Mbyte 22-bit parity/CSR MOS RAM
M7554 KDJ11-DA J11 CPU 15 MHz, 512-Kbyte RAM, 2 SLUs, LTC
M7554-01 KDJ11-DA J11 CPU 15 MHz, 512-Kbyte RAM, 2 SLUs, LTC (VE)
M7554-02 KDJ11-DB 11/53-PLUS CPU
M7554-04 KDJ11-DD J11 CPU 18 MHz, 1.5-Mbyte RAM, 2 SLUs (CSS)
M7554-PA KDJ11-SA J11 CPU 15 MHz, 512-Kbyte RAM, 2 SLUs, S-box handle
M7554-PB KDJ11-SB J11 CPU 18 MHz, 512-Kbyte RAM, 2 SLUs, LAT PROM,
M7554-PC CMR53-AA J11 CPU 18 MHz, 512-Kbyte RAM, 2 SLUs, S-box handle,
M7554-SA KDJ11-SA J11 CPU 15 MHz, 512-Kbyte RAM, 2 SLUs, S-box handle
M7554-SC KDJ11-SC J11 CPU 15 MHz, 512-Kbyte RAM, 2 SLUs, S-box handle
M7554-SD KDJ11-SD J11 CPU 18 MHz, 1.5-Mbyte RAM, LAT ROM, S-box handle
M7554-SE KDJ11-SE J11 CPU 18 MHz, 1.5-Mbyte RAM, 2 SLUs, LTC, S-box
M7554-YA KDJ11-SA J11 CPU 15 MHz, 512-Kbyte RAM, 2 SLUs, LTC,
M7554-YB KDJ11-SB J11 CPU 15 MHz, 512-Kbyte RAM, 2 SLUs, LAT PROMs,
M7555 RQDX3 Winchester and floppy disk controller
M7555-YA RQDX3-SD Controller for RX33D 48TPI floppy disk drive
M7558 2-Mbyte 22-bit MOS memory
M7558-AA MSV11-SA 2-Mbyte 22-bit parity/CSR MOS RAM
M7559 TQK70 TMSCP controller for TK70
M7573 RQDX4 Controller for RX35, RD50/1/2/3/4
M7602 QVSS Q-bus Video Sub System module for Q22 systems
M7602-YA QVSS Q-bus Video Sub System module, bitmap graphics
M7605 TQK25 0.25" streaming tape drive controller (TK25)
M7606-AA KA630-AA microVAX II with 1-Mbyte, floating point, time of year clock, boot/diagnostic ROM (Q22-bus)
M7607-AA MS630-AA 1-Mbyte RAM for microVAX II (Q-22 via CD)
M7608-AA MS630-BA 2-Mbyte RAM for microVAX II (Q-22 via CD)
M7608-BA MS630-BB 4-Mbyte RAM for microVAX II (Q22-bus)
M7609-AA MS630-CA 8-Mbyte parity 36-bit RAM for microVAX II (Also M7609-AC, -AF, -AH, -AP, -AV) (Q-22 via CD)
M7616 J11 CPU, 512-Kbyte RAM, 64-Kbyte PROM (Q22 peripheral processor)
M7620 KA650-AA/BA microVAX III CPU (-AA full license, -BA
M7621 MS650-AA 8MB RAM for KA650
M7622 MS650-BA 16MB RAM for KA650
M7625 KA655-BA microVAX III CPU (workstation license), 60nS
M7626 KA660 VAX 4000 CPU, 57 MHz Q-22 DSSI ethernet
M7635-AA KN210 RISC 3000 CPU, Q-bus interface
M7635-AB KN210 M7635-AA with LSI R3000, R3020 chips
M7635-AC KN210 M7635-AA with PERF R3000, R3020 chips
M7651 DRV11-WA 18/22-bit DMA general purpose parallel interface
M7651-YB DRV11-WA M7651, revision C ciruit
M7656 VSV21-AA Colour graphics module: M68K processor, HD63486
M7676 KXT11-AB Single-board 16-bit dual-height CPU.
M7679 ISDN ISDN basic rate access Q-bus board
M7740 RQC25 Q22-bus to LESI bus adaptor used on disks with Also M7740-01, -PA) (Also called KLESI-QA)
M7940-YA DLV11 M7940 with extra wires to bring out clock &
M7940-YC DLV11 Modified M7940 for use in a tester, TTL in/out
M7940-YD DLV11 Modified M7940 for use in a tester, switchable
M7940-YE DLV11 Modified M7940 for use in a tester, XON/XOFF
M7941 DRV11 16-bit parallel line unit
M7942 MRV11-AA Space for 4K 16-bit PROM
M7942-YA MRV11-VA VT71T bootstrap
M7942-YB MRV11-AA M7942 with VT52 emulator, VT71 bootstrap
M7942-YC MRV11-VC VT72 bootstrap/diagnostic module
M7942-YD MRV11-AA M7942 with CSR11 bootstrap
M7944 MSV11-B 4-Kword 16-bit MOS RAM (external refresh)
M7946 RXV11 RX01 floppy disk controller
M7948 DRV11-P LSI-11 bus foundation module. Basic Q-bus
M7949 LAV11 LA180 line printer control module
M7950 DRV11-B 16-bit DMA parallel general purpose interface
M7951 DUV11-DA Sync interface, character protocol; DU11-DA compat.
M7952 KWV11-A Programmable realtime clock
M7953 MNCKW MINC programmable real time clock
M7954 IBV11 IEC general purpose interface (GPIB)
M7955-AD MSV11-CD 16-Kword 16-bit MOS RAM with on-board refresh
M7957 DZV11 4-line double-buffered async EIA MUX
M8006-PA 72-bit opto-isolated output module
M8007-PA 72-bit opto-isolated input module
M8012 BDV11 Bootstrap, power on self test, load program from Eproms and terminator card
M8013 RLV11 RL01 disk controller, 1 of 2
M8014 RLV11 RL01 bus controller, 2 of 2
M8016 KPV11-A Power fail, realtime clock, no termination
M8016-YB KPV11-B M8016 with 120-ohm termination
M8016-YC KPV11-C M8016 with 250-ohm termination
M8017-AA DLV11-E/EC Single-line async control module
M8017-PA DLV11-E/EC Single-line async control module, S-box handle
M8018 KUV11-AA Writable control store module
M8020 DPV11-M Single-line serial EIA sync interface
M8020-PA DPV11-SA Single-line serial sync interface, S-box handle
M8021 MRV11-BA 256-word RAM, space for 4-Kword UV PROM
M8027 LPV11 Printer interface module
M8028 DLV11-F Async interface EIA/20ma, error flags, break bit
M8029 RXV21 RX02 floppy disk drive control module
M8043 DLV11-J 4-SLU peripheral interface
M8044-AA MSV11-DA 4-Kword 16-bit MOS RAM (Also M8044-AB, -AC, -AD)
M8044-BA MSV11-DB 8-Kword 16-bit MOS RAM (Also M8044-BB, -BC, -BD)
M8044-CA MSV11-DC 16-Kword 16-bit MOS RAM
M8044-DA MSV11-DD 32-Kword 16-bit MOS RAM
M8045-AB MSV11-EA 4-Kword 18-bit MOS RAM
M8045-CH MSV11-EC 16-Kword 18-bit MOS RAM (Also M8045-CJ, -CK, -CL)
M8045-DA MSV11-ED 32-Kword 18-bit MOS RAM
M8047-AA MXV11-AA 4-Kword RAM, 2 async EIA SLU, sockets for 2
M8047-CA MXV11-AC 16-Kword RAM, 2 async EIA SLU, sockets for 2
M8047-HA MXV11-HA 16-Kword RAM, 2 async EIA SLU (8 bits + parity),
M8048 MRV11-C Universal PROM/ROM module with sockets for 16
M8049 DRV11-J Hi-density parallel line unit (4 lines)
M8049-AA DRV1J-SA/SF Modification of DRV11-J to DRV1J-SA/-SF
M8049-PA DRV11-J M8049 with S-box handle
M8053 DMV11 Microprogrammed controller V.35, RS232/423, with
M8053-AA DMV11 Microprogrammed controller (needs one of M5930-
M8053-MA DMV11-A M8053 with DDCMP control ROM (point-to-point or
M8053-PA DMV11 M8053 with S-box handle
M8059-FA MSV11-LF 64-Kword MOS RAM, single voltage
M8059-KA MSV11-LK 128-Kword MOS RAM, single voltage
M8061 RLV12 RL01/RL02 disk control, 22-bit address
M8063-AA KXT11-AA FALCON (SBC-11/21) single-board CPU with 2 SLU, 1 parallel line unit, line frequency clock,
M8063-BA KXT11-BA FALCON (SBC-11/21) single-board CPU with 2 SLU, 1 parallel line unit, line frequency clock,
M8064 DMV11 Microprogrammed controller, integral modem, space
M8064-MA DMV11 M8064 with DDCMP point-to-point or multidrop,
M8067-FA MSV11-PF 128-Kbyte MOS memory with parity CSR
M8067-KA MSV11-PK 256-kbyte MOS memory with parity CSR
M8067-LA MSV11-PL 512-Kbyte MOS memory with parity CSR
M8185-YC KDF11-AC 11/23 CPU without options
M8186-YA KDF11-AA 11/23 CPU with KTF11-AA (MMU) and sockets for
M8186-YB KDF11-AB 11/23 CPU with KTF11-AA (MMU) AND KEF11-AA (FP11)
M8186-YC KDF11-AC 11/23 CPU without options
M8188 FPF11 Floating point processor
M8189 KDF11-BA 11/23-PLUS single-board CPU
M8190-AB KDJ11-BB J11 CPU 15 MHz with 2 boot & diagnostic ROMs, FPJ11
M8190-AC KDJ11-BD J11 CPU 15 MHz with 2 boot & diagnostic ROMs,
M8190-AD KDJ11-BA J11 CPU 18 MHz with 2 boot & diagnostic ROMs, FPJ11
M8190-AE KDJ11-BF Q/U 11/83-84 CPU J11 CPU 18 MHz with 2 boot & diagnostic
M8192 KDJ11-A LSI-11/73 CPU
M8192-YB KDJ11-AB LSI-11/73 CPU 8-Kbyte cache, FPJ11-AA compatible,
M8192-YC KDJ11-AC LSI-11/73 CPU 8-Kbyte cache with FPJ11-AA, no
M8194 KDF11 Data memory module
M8195 KDF11 Cache data path module
M8217 DW11-A UNIBUS to Q-bus interface module
M8377 KXT11-CA T11 16-bit single-board computer. Q-bus with a host processor
M8392-AA 68020, 1-Mbyte, 2 x 8-channel UARTs
M8392-BA 68020, 1-Mbyte, 2 x 8-channel UARTs, S-box handle
M8578 MRV11-D PROM/ROM module with 16 sockets; 24/28-pin devices Requires MXV11-B2 bootstrap ROM for bootstrapping
M8631-AA MCV11-DA 4-Kword 16-bit 2Kx8 static CMOS RAM with 96-hour battery backup (Also M8631-AF, -AL) (Q22-bus)
M8631-CA MCV11-DC 16-Kword 16-bit 2kx8 static CMOS RAM with 96-hour battery backup (Also M8631-CF, -CL) (Q22-bus)
M8634 IEQ11-A DMA version of IEEE(GPIB) interface
M8637-BA MSV11-JB 1-Mbyte ECC PMI RAM with CSR (Q22-bus)
M8637-CA MSV11-JC 2-Mbyte ECC PMI RAM with CSR (Q22-bus)
M8637-DA MSV11-JD 1-Mbyte ECC RAM
M8637-EA MSV11-JE 2-Mbyte ECC RAM
M8638 HDLC DMA single channel sync MUX controller
M8639-YA RQDX1 RD51/52 & RX50 control module
M8639-YB RQDX2 RD51/52 & RX50 control module, can be expanded
M8981-AA KDJ11-EA Q/U 11/93-94 CPU 18 MHz, DCJ11, FPJ11, 2-Mbyte parity
M8981-BA KDJ11-EB Q/U 11/93-94 CPU 18 MHz, DCJ11, FPJ11, 4-Mbyte parity
M9037 Grant continuity
M9047 Grant continuity (also M9047-SA, -SF)
M9058 Distribution/adaptor/buffer board for RQDX1/2/3
M9400-YA REV11-A 120-ohm terminators with refresh & floppy boot
M9400-YB TEV11 120-ohm terminators
M9400-YC REV11-C Refresh and boot alone
M9400-YD REV11-D Headers alone
M9400-YE REV11-E Headers and 250-ohm terminators can be used with M9401 as a Q-bus extender
M9400-YF REV11-F M9400-YA with boot sockets with no ROMs
M9400-YH REV11-H LDP/COMM boot & floppy boot with terminators
M9400-YJ REV11-J DMA refresh bootstrap, cable connector, 250-ohm
M9400-YK REV11-K M9400-YH with no terminators
M9400-YL REV11-L M9400-YH with cable connectors
M9400-YM REV11-M Refresh with DECnet bootstrap
M9400-YN REV11-N RX02 boot and refresh
M9401 Mirror-image connector used at other end of cable
M9404 1st Q22-bus cable connector, no terminators
M9404-YA Cable connector for expansion box, with 240-Ohm
M9405 2nd Q22-bus cable connector, no terminators, mirror
M9405-YA M9405 with 120-Ohm terminators

External links[edit]

References[edit]

  1. ^ Schmidt, Atlant G.,Unibus,Q-Bus and VAXBI Bus, in Di Giacomo Joseph Ed., McGraw Hill, 1990
  2. ^ Microcomputer Products Handbook, Digital,1985