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The QCDPAX was a processor array designed and built jointly by the University of Tsukuba and Anritsu Corporation for the simulation of the lattice QCD.

PAX (Processor Array eXperiment) was the name of the series of the parallel computers since 1977 for the study of parallel high-speed computation in scientific and engineering applications. The first and second machines were made at Kyoto University in 1978 and 1980 respectively, and the project was moved to the University of Tsukuba in 1981. It utilized the MIMD processor array architecture with the two-dimensional nearest-neighbor connection and the broadcasting bus.

QCDPAX was the fifth model in the PAX series. A prototype with four processing units was constructed in the April 1988, and a practical system with 288 processing units was built in the April 1989. In the spring of 1990, it was increased with PU number to 480 and achieved a peak speed of 14GFLOPS.

Each processing unit was an independent one-board microcomputer. Motorola's microprocessor MC68020 (25MHz) was used as the CPU. The local memory was 4MBytes with 100ns 1Mbit DRAM. The QCDPAX utilized LSI Logic's floating-point processing unit L64133 on the market. L64133 had peak performance of the 33MFLOPS. The floating-point processing unit controller, newly developed by the gate array, was also utilized to derive the performance from the FPU by controlling the direct memory access between the data memory and floating-point processing unit.[1][2][3]


  1. ^ T.Shirakawa, T.Hoshino, Y.Oyanagi, Y.Iwasaki, T.Yoshie, K.Kanaya, S.Ichii, and T.Kawai "QCDPAX - An MIMD Array of Vector Processors for the Numerical Simulation of Quantum Chromodynamics", IEEE & ACM Proc. Supercomputing '89, Reno Nevada, Nov. (1989) pp.495-504.
  2. ^ Y.Iwasaki, T.Hoshino, T.Shirakawa, Y.Oyanagi, and T.Kawai "QCDPAX: A parallel computer for lattice QCD simulation", Comp. Phys. Comm. 49 (1988) pp.449-455.
  3. ^ D. Kahaner "Computer Science Research Activities in Asia", Diane Publishing Company, 1993.

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