R3000

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The R3000 is a full 32 bit RISC microprocessor chip set developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture (ISA). Introduced in June 1988, it was the second MIPS implementation, succeeding the R2000 as the flagship MIPS microprocessor. It operated at 20, 25 and 33.33 MHz.

The MIPS 1 instruction set is very small compared to the instruction sets of other microprocessors, such as the contemporary 80x86, 680x0 architectures), as it includes only most commonly used instructions and supports very limited number of addressing modes. The small number of CPU instructions, as well as other instruction set features—fixed instruction length and only three different types of instruction formats—greatly simplify instruction decoding and processing. To speed up processing even further the CPU employs a 5-stage instruction pipeline. The pipeline design allows the R3000 CPU to execute most instructions at a rate close to 1 instruction per cycle.

In addition to the CPU core, the R3000 microprocessor includes a Control Processor (CP), which contains a Translation Lookaside Buffer and a Memory Management Unit. The CP works as a coprocessor. Besides the CP, the R3000 can also support an external R3010 numeric coprocessor and two other external coprocessors.

The R3000 CPU does not include its own level 1 cache. Instead, the processor has an on-chip cache controller which controls separate external data and instruction caches. The size of each external cache can be as large as 256 KB. The CPU can access both caches during the same CPU cycle.

The R3000 found much success and was used by many companies in their workstations and servers. Users included:

The R3000 was also used as a high-end embedded microprocessor, and when advances in technology rendered it obsolete for high-performance systems, it was used as a low-cost embedded design. Companies such as LSI Logic developed derivatives of the R3000 specifically for embedded systems.

The R3000 was a further development of the R2000 with minor improvements including larger translation lookaside buffer and faster bus to the external caches. The R3000 die contained 115,000 transistors and measured 56 mm2. MIPS was a fabless semiconductor company, so the R3000 was fabricated by MIPS partners including Integrated Device Technology (IDT), LSI Logic, NEC Corporation, Performance Semiconductor, and others. It was fabricated in a 1.2 µm complementary metal–oxide–semiconductor (CMOS) process with two levels of aluminium interconnect.

MIPS R3000A die shot

Derivatives of the R3000 for non-embedded applications include:

  • R3000A - A further development by MIPS introduced in 1989. It operated at high clock frequencies of 20, 25, 33.33 and 40 MHz.
  • PR3400 - Developed by Performance Semiconductor, introduced in May 1991 at 25, 33 and 40 MHz. It is an integrated version containing the Performance Semiconductor PR3000A and PR3010A on a single die.

Derivatives of the R3000 for embedded applications include:

  • PR31700 - A 75 MHz microcontroller from Philips Semiconductors. It is fabricated in a 0.35 μm process and is packaged in a 208-pin LQFP. It uses a 3.3 W power supply and dissipates 0.35 W.
  • RISController - A family of low-end microcontrollers from IDT. Models include the R3041, R3051, R3052, and R3081.
  • TX3900 - A microcontroller from Toshiba.
  • Mongoose-V - A radiation-hardened and expanded 10–15 MHz CPU for spacecraft onboard computers.

References[edit]

Further reading[edit]

  • Chris Rowen, Mark Johnson, Paul Ries, "The MIPS R3010 Floating-Point Coprocessor," IEEE Micro, vol. 8, no. 3, pp. 53–62, May/June 1988.