Reference Verification Methodology

The Reference Verification Methodology (RVM) is a complete set of metrics and methods for performing Functional verification of complex designs such as for Application-specific integrated circuits or other semiconductor devices. It was published by Synopsys in 2003.

RVM is implemented under OpenVera.

The SystemVerilog implementation of the RVM is known as the VMM (Verification Methodology Manual). It contains a small library of base classes.

References

• OVM/UVM Verification Methodology at the Verification Academy
• Verification Methodology Manual for SystemVerilog
• vmmcenter.org
• RVM Testbench Example