Resistive random-access memory

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Resistive random-access memory (RRAM or ReRAM) is a non-volatile memory type under development by a number of different companies, some of which have patented versions of ReRAM.[1][2][3][4][5][6][7] The technology bears some similarities to CBRAM and phase change memory.

In February 2012 Rambus bought a ReRAM company called Unity Semiconductor for $35 million.[8] Panasonic launched a ReRAM evaluation kit in May 2012, based on a tantalum oxide 1T1R (1 transistor - 1 resistor) memory cell architecture.[9]

In 2013, Crossbar introduced a prototype of RRAM as a chip about the size of a postage stamp that can store 1 TB of data. According to an August 2013 interview with Crossbar, the large-scale production of their RRAM chips is scheduled for 2015.[10]

Different forms of ReRAM have been disclosed, based on different dielectric materials, spanning from perovskites to transition metal oxides to chalcogenides. Even silicon dioxide has been shown to exhibit resistive switching as early as 1967,[11] and has recently been revisited.[12][13]

Leon Chua, who is considered to be the father of non-linear circuit theory, has argued that all 2-terminal non-volatile memory devices including ReRAM should be considered memristors.[14] Stan Williams of HP Labs has also argued that all ReRAM should be considered to be a memristor.[15] These claims, however, seem not to be justified given that the memristor theory in itself is open to question.[16][17] There is an ongoing discussion whether or not redox-based resistively switching elements (ReRAM) are covered by the current memristor theory.[18]


The basic idea is that a dielectric, which is normally insulating, can be made to conduct through a filament or conduction path formed after application of a sufficiently high voltage. The conduction path formation can arise from different mechanisms, including defects, metal migration, etc. Once the filament is formed, it may be reset (broken, resulting in high resistance) or set (re-formed, resulting in lower resistance) by an appropriately applied voltage. Recent data suggest that many current paths, rather than a single filament, are probably involved.[19]

A memory cell can be produced from the basic switching element in three different ways. In the simplest approach, the single memory element can be used as a basic memory cell, and inserted into a configuration in which parallel bitlines are crossed by perpendicular wordlines with the switching material placed between wordline and bitline at every cross-point. This configuration is called a cross-point cell. Since this architecture can lead to a large "sneak" parasitic current flowing through non selected memory cells via neighboring cells, the cross-point array may have a very slow read access. A selection element can be added to improve the situation, but this selection element consumes extra voltage and power. A series connection of a diode in every cross-point allows to reverse bias, zero bias, or at least partial bias non selected cells, leading to negligible sneak currents. This can be arranged in a similar compact manner as the basic cross-point cell. Finally a transistor device (ideally a MOS Transistor) can be added which makes the selection of a cell very easy and therefore gives the best random access time, but comes at the price of increased area consumption.

For random access type memories, a transistor type architecture is preferred while the cross-point architecture and the diode architecture open the path toward stacking memory layers on top of each other and therefore are ideally suited for mass storage devices. The switching mechanism itself can be classified in different dimensions. First there are effects where the polarity between switching from the low to the high resistance level (reset operation) is reversed compared to the switching between the high and the low resistance level (set operation). These effects are called bipolar switching effects. On the contrary, there are also unipolar switching effects where both set and reset operations require the same polarity, but different voltage magnitude.

Another way to distinguish switching effects is based on the localization of the low resistive path. Many resistive switching effects show a filamentary behavior, where only one or a few very narrow low resistive paths exist in the low resistive state. In contrast, also homogenous switching of the whole area can be observed. Both effects can occur either throughout the entire distance between the electrodes or happen only in proximity to one of the electrodes. Filamentary and homogenous switching effects can be distinguished by measuring the area dependence of the low resistance state.[20]

Material systems for resistive memory cells[edit]

A large number of inorganic and organic material systems showing thermal or ionic resistive switching effects have been demonstrated in the literature. These can be grouped into the following categories:[20]

  • phase change chalcogenides like Ge2Sb2Te5 or AgInSbTe
  • binary transition metal oxides like NiO or TiO2
  • perovskites like Sr(Zr)TiO3 or PCMO
  • solid-state electrolytes like GeS, GeSe, SiOx or Cu2S
  • organic charge transfer complexes like CuTCNQ
  • organic donor–acceptor systems like Al AIDCN
  • various molecular systems


Papers at the IEDM Conference in 2007 suggested for the first time that ReRAM exhibits lower programming currents than PRAM or MRAM without sacrificing programming performance, retention or endurance.[21] On April 30, 2008 HP announced that they had discovered the memristor, originally envisioned as a missing 4th fundamental circuit element by Leon Chua in 1971. On July 8 they announced they would begin prototyping ReRAM using their memristors.[22] At IEDM 2008, the highest performance ReRAM technology to date was demonstrated by ITRI,[23] showing switching times less than 10 ns and currents less than 30 microamps. At IEDM 2010, ITRI also broke the speed record, showing <0.3 ns switching time, while also showing process and operation improvements to allow yield up to 100%.[24] Also, IMEC presented several updates of their ReRAM program at the 2012 Symposia on VLSI Technology and Circuits, including a solution with a 500nA operating current.[25]

Future applications[edit]

ReRAM has the potential to become the front runner among other non-volatile memories. Compared to PRAM, ReRAM operates at a faster timescale (switching time can be less than 10 ns), while compared to MRAM, it has a simpler, smaller cell structure (less than 8F² MIM stack). There is a type of vertical 1D1R (one diode, one resistive switching device) integration used for crossbar memory structure to reduce the unit cell size to 4F² (F is the feature dimension).[26] Compared to flash memory and racetrack memory, a lower voltage is sufficient and hence it can be used in low power applications.

ITRI has recently shown that ReRAM is scalable below 30 nm.[27] The motion of oxygen atoms is a key phenomenon for oxide-based ReRAM;[28] one study has indicated that oxygen motion may take place in regions as small as 2 nm.[29] It is believed that if a filament is responsible, it would not exhibit direct scaling with cell size.[30] Instead, the current compliance limit (set by an outside resistor, for example) could define the current-carrying capacity of the filament.[31]

A significant hurdle to realizing the potential of ReRAM is the sneak path problem which occurs in larger passive arrays. In 2010, complementary resistive switching (CRS) was introduced as a possible solution to the interference from sneak-path currents.[32] In the CRS approach, the information storing states are pairs of high and low resistance states (HRS/LRS and LRS/HRS) so that the overall resistance is always high, allowing for larger passive crossbar arrays.

A drawback to the initial CRS solution is the high requirement for switching endurance caused by conventional destructive readout based on current measurements. A new approach for a nondestructive readout based on capacity measurement potentially lowers the requirements for both material endurance and power consumption.[33] Bi-layer structure is used to produce the nonlinearity in LRS to avoid the sneak path problem.[34] Single layer device exhibiting a strong nonlinear conduction in LRS has been recently reported.[35] Another bi-layer structure is introduced for bipolar ReRAM to improve the HRS and stability of the memory endurance performance.[36]


  1. ^ U.S. Patent 6,531,371
  2. ^ U.S. Patent 7,292,469
  3. ^ U.S. Patent 6,867,996
  4. ^ U.S. Patent 7,157,750
  5. ^ U.S. Patent 7,067,865
  6. ^ U.S. Patent 6,946,702
  7. ^ U.S. Patent 6,870,755
  8. ^ Mellor, Chris (7 February 2012), Rambus drops $35m for Unity Semiconductor 
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  16. ^ Meuffels, P.; Soni, R. (2012), "Fundamental Issues and Problems in the Realization of Memristors", arXiv, arXiv:1207.7319, Bibcode:2012arXiv1207.7319M 
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  28. ^ New Non-Volatile Memory Workshop 2008, Hsinchu, Taiwan.
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