Rock (processor)

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UltraSPARC Rock Processor

Designed by	Sun Microsystems
Instruction set	SPARC V9
Cores	16

Rock is a multithreading, multicore, SPARC microprocessor developed at Sun Microsystems. It is a separate development from the Niagara (UltraSPARC T1 and T2) family.

Rock aimed at higher per-thread performance, higher floating-point performance, and greater SMP scalability than the Niagara family. The Rock processor targeted traditional high-end data-facing workloads, such as back-end database servers, as well as floating-point intensive high-performance computing workloads, whereas the Niagara family targets network-facing workloads such as web servers.

Contents 1 Processor core 1.1 Core cluster 2 Unconventional features 3 Server platforms 3.1 Physical resources 3.2 Input/output description 3.3 Input/output expandibility 3.4 Common features 3.5 AT7180 3.6 AT7280 3.7 AT7480 3.8 AT7880 4 Product pre-release history 5 References 6 Further reading

[edit] Processor core

The Rock processor implements the 64-bit SPARC V9 instruction set and the VIS 3.0 SIMD multimedia instruction set extension.^[1] Each Rock processor has 16 cores, with each core capable of running two threads simultaneously, yielding 32 threads per chip. Servers built with Rock use FB-DIMMs to increase reliability, speed and density of memory systems. The Rock processor uses a 65 nm manufacturing process for a design frequency of 2.3 GHz.^[2] The maximum power consumption of the Rock processor chip is approximately 250 W.^[3]

[edit] Core cluster

The 16 cores in Rock are arranged in four core clusters. The cores in a cluster share a 32 KB instruction cache, two 32 KB data caches, and two floating point units. Sun designed the chip this way because server workloads usually have high re-utilization in data and instruction across processes and threads but low number of floating-point operations in general. Thus sharing hardware resources among the four cores in a cluster leads to significant savings in area and power but low impact to performance.^[4]

[edit] Unconventional features

In 2005, Sun publicly disclosed a feature in the Rock processor called hardware scout. Hardware scout uses otherwise idle chip execution resources to perform prefetching during cache misses.^[5]

In March 2006, Marc Tremblay, Vice President and Chief Architect for Sun's Scalable Systems Group, gave a presentation at the Xerox Palo Alto Research Center (PARC) on thread-level parallelism, hardware scouting, and thread-level speculation.^[6] These multithreading technologies were expected to be included in the Rock processor.

In August 2007, Sun confirmed that Rock would be the first production processor to support transactional memory.^[7] To provide the functionality, two new instructions were introduced (chkpt, commit) with one new status register (cps). The instruction chkpt <fail_pc> is used to begin a transaction and commit to commit the transaction. If transaction abort condition is detected, jump to <fail_pc> is issued and cps can be used to determine the reason. The support is best-effort based, as in addition to data conflicts, transactions can be aborted by other reasons. These include TLB misses, interrupts, certain commonly used function call sequences and "difficult" instructions (e.g., division).^[8] Nevertheless, many (arguably fine-grained) code blocks requiring synchronization could have benefited from transactional memory support of the Rock processor.^[9]

In February 2008, Marc Tremblay announce a unique feature called "out-of-order retirement" at the ISSCC. The benefits include replacing the "traditional instruction window with this much smaller deferred queue".^[10]

In April 2008, Sun engineers presented the transactional memory interface at Transact 2008, and the Adaptive Transactional Memory Test Platform simulator was announced to be made available to the general public shortly after.^[8][11]

[edit] Server platforms

The Rock processor slots into the code-named Supernova (server) line. Details of the server specifications were released into Open Solaris Architecture Review^[12]

[edit] Physical resources

The Physical Resource Inventory (PRI) of the ARC 2008/761 indicates the Supernova platforms will support: IEEE 1275 OpenFirmware, platform virtualization through Logical Domains (LDOM), independent system controller (SC), and Fault Management Architecture (FMA) Domain Services.^[13] The FMA feature was originally referenced to FWARC/2006/141, but this was closed and extended in FWARC/2008/455 "to successfully diagnose PCI fabric errors that occur in root domains."^[14]

[edit] Input/output description

The iodevice Machine Description (MD) Node Specification of ARC 2008/761 indicates support for both PCI Express (PCIe) hot-pluggable slots as well as a bridge to older PCI eXtended (PCI-X)).^[15]

[edit] Input/output expandibility

Hitendra Zhangada described a variety of PCIe parameters in software which support the hardware platforms. Bronze servers would support PCIe slots 0-5. Silver servers would support I/O boards 0-1 and PCIe slots 0-7 for each board. Platinum servers support I/O boards 0-3 and PCIe slots 0-7 for each board. Silver-II servers support PCIe slots 00-19. Platinum-II servers support boards 0-7 and slots 0-3 for each board.^[16]

[edit] Common features

Hitendra Zhangada, SPS Common SW Features Engineering, at Software Group, Sun Microsystems, Inc. wrote an email on December 9 in 2008 sponsoring a fast-track software ARC case describing Supernova platforms AT480 and AT880. Ravi Subbarao of Sun Microsystems, Director of Enterprise Systems Software, sponsored ARC 2008/761. The email described platforms bindings and interface changes: in MD, PRI and OpenBoot device node.^[16]

[edit] AT7180

There is a speculated Sparc Enterprise AT7180, as a single socket model. It is a future model speculated to handle as many as 32 hardware threads.^[17]

[edit] AT7280

There is a speculated Sparc Enterprise AT7280, as a dual socket model. It is a future model speculated to handle as many as 64 hardware threads.^[18]

[edit] AT7480

The Supernova Silver-II model received the name Sparc Enterprise AT7480 is a quad socket model. It is a future model reported to handle as many as 128 hardware threads.^[19] The AT7480 is based upon the PCI Express bus architecture with an OpenFirmware.

[edit] AT7880

The Supernova Platinum-II model received the name Sparc Enterprise AT7880 is an octal socket model. It is a future model reported to handle as many as 256 hardware threads.^[20] The AT7880 is based upon the PCI Express bus architecture with an OpenBoot firmware. Pingchung Lee, Responsible Engineer for ARC 2008/761 explains in a December 10 email in 2008 that the AT7880 has eight individual CPU boards and each CPU board has one Sun Neptune multithreaded 10 Gigabit Ethernet chip on-board.^[21]

[edit] Product pre-release history

In February 2005, Sun CEO Scott McNealy discussed the "taping out" of Rock to be on schedule for later in 2005.^[22]

In January 2007, Sun announced the tape-out of Rock.^[23]

In April 2007, Sun CEO Jonathan I. Schwartz blogged an image of a fabricated and BGA-packaged Rock chip, labeled UltraSPARC RK, and disclosed that it could address 256 terabytes of virtual memory in a single system running Solaris.^[24]

In May 2007, Sun announced the first silicon of Rock booting Solaris successfully.^[25]

In August 2007, details on the use of Transactional Memory in the Rock architecture were explained.^[26]

In December 2007, Sun announced that Rock would be delayed from 2008 until 2009 due to "entirely new design and given its uniqueness and complexity".^[27]

In 2008, Mark Moir presented at Sun Labs Open House 2008 Rock's Transactional Memory and How to Exploit It, discussing Transactional Memory as well as Scouting Threads and how these mitigated the computing problems not solved by innovative use of massive thread counts of slower processors.^[28]

In September 2008, OpenSolaris project started to organize patches for the SuperNova platforms, which use the RocK processor.^[29]

In January 2009, Sun CEO Jonathan Schwartz announced Rock was still on track for a 2009 release.^[30]

On Tuesday, 10 March 2009 at 10:30-11:30am, Dave Dice, Yossi Lev, Mark Moir and Dan Nussbaum presented a published a paper Early Experience with a Commercial Hardware Transactional Memory Implementation at the Fourteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '09) during Session 5 Transactional Memories chaired by Jim Goodman, in Washington DC. They published their "experience with the hardware transactional memory (HTM) feature of two pre-production revisions of a new commercial multicore processor" by Sun Microsystems referred to as Rock.^[31][32][33]

In May 2009, Mark Moir, Principal Investigator of Scalable Synchronization Research Group of Sun Laboratories in conjunction with Dave Dice, Yossi Lev, and Dan Nussbaum published the paper "Early Experience With a Commercial Hardware Transactional Memory Implementation."^[34]

On 12 June 2009, a posting announced a technical NDA only presentation on ROCK at the Hamburg OpenSolaris Users Group Meeting on July 14, 2009 in Germany via a Sun blog.^[35]

On 15 June 2009, The New York Times reported that "two people briefed on Sun’s plans" said the Rock project was canceled. Sun is refusing to comment on information given to The New York Times that the Rock project has been canceled.^[36][37]

On 17 June 2009, The EE Times reported that "Sun did not submit a paper on Rock... leading to speculation the company may have canceled the chip."^[38]

On Wednesday, 24 June 2009, a presentation on Speculative Threading & Parallelization featured A Novel Pipeline Architecture Implemented in Sun's ROCK Processor at The 36th International Symposium on Computer Architecture.^[39]

On 6 August 2009, the support for the Rock-CPU was removed from the OpenSolaris Project.^[40]

On Thursday, 13 August 2009 between 8:20am-9:35am, a presentation on NZTM: Nonblocking Zero-indirection Transactional Memory written by Fuad Tabba, Mark Moir, James Goodman, Andrew Hay, and Cong Wang is scheduled to be presented at the 21st ACM Symposium on Parallelism in Algorithms and Architectures in Calgary, Canada during the Transactional Memory II session chaired by Tatiana Shpeisman. The NZSTM algorithm performance was evaluated on Sun’s forthcoming Rock processor.^[41][42]

On Tuesday, 15 September 2009 between 1:30-3:00, the paper tm_db: A Generic Debugging Library for Transactional Programs written by Yossi Lev and Maurice Herlihy is scheduled to be presented at The Eighteenth International Conference on Parallel Architectures and Compilation Techniques (PACT) Raleigh, North Carolina during the Tools and Testing session chaired by Rob Fowler.^[43][44]

On 11 September 2009, The Register reported that the Rock processor was left out of the SPARC processor roadmap shown to Sun's customers and partners.^[45]

[edit] References

[edit] Further reading

• "Sun's Rock CPU Could Be a Gem for Oracle". IEEE Spectrum. 2009-06-01. http://spectrum.ieee.org/jun09/9230. 

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