The SPARC64 VI, code-named Olympus-C, is a microprocessor, developed by Fujitsu. It implements the SPARC V9 instruction set architecture (ISA) and is compliant with the Joint Programming Specification (JSP1) developed by Fujitsu and Sun. It is used by Fujitsu and Sun Microsystems in their SPARC Enterprise M-class servers. The SPARC64 VI was succeeded by the SPARC64 VII (previously called the SPARC64 VI+) in July 2008.
The SPARC64 VI implements multithreading using two techniques, chip multiprocessing (CMP) and coarse-grained multi-threading which Fujitsu calls vertical multi-threading (VMT). The two cores both execute one thread each simultaneously, implementing CMP. Each core executes two threads, but only one of the two concurrent threads is executed at any given time. Which thread is executed is determined by time sharing or if the thread is executing a long latency operation, prompting the pipeline switches to another thread. Multithreading required duplication of the integer registers, floating-point registers, control registers and program counters so there is one set of each for every thread.
As the SPARC64 VI is a dual-core microprocessor, bandwidth had to be increased if the extra core is to contribute to performance significantly. The cores share a 6 MB on-die unified L2 cache. The L2 cache is 12-way set associative and has a 256-byte line size. The cache is accessed by two unidirectional buses. The read bus, which delivers data to the cores, is 256 bits wide; and the write bus is 128-bit wide. It also uses a new system bus, the Jupiter Bus.
The SPARC64 VI is the first SPARC microprocessor implementing a fused multiply–add (FMA), while the corresponding instructions performed separate multiplication and addition operations in previous versions.
The SPARC64 VI consisted of 540 million transistors. The die measures 20.38 mm by 20.67 mm for an area of 421.25 mm2. It is fabricated by Fujitsu in a 90 nm, 10-layer copper, complementary metal–oxide–semiconductor (CMOS) silicon on insulator (SOI) process.
The SPARC64 VII, code-named Jupiter, is a further development of the SPARC64 VI. It is a quad-core microprocessor. Each core is capable of two-way simultaneous multithreading (SMT), which replaces two-way coarse-grained multithreading, termed vertical multithreading (VMT) by Fujitsu. Thus, it can execute eight threads simultaneously.
Other changes include more RAS features. The integer register file is now protected by ECC, and the number of error checkers has been increased to around 3,400.
It consists of 600 million transistors and is fabricated by Fujitsu in a 65 nm CMOS process.
The SPARC64 VII is socket compatible with its predecessor, the SPARC64 VI. Existing M-class servers are able to upgrade to the SPARC64 VII processors in the field.
The SPARC64 VII+, code-named Jupiter-E, is a further development of the SPARC64 VII. The VII+ holds the following features in common with the VII include: both are quad-core microprocessors where each core is capable of two-way simultaneous multithreading (SMT); a single socket can execute eight threads simultaneously; each core gets 128 KB Level 1 cache.
Changes includes running at 3 GHz and containing 12 MB of Level 2 cache. The 50% increase in cache and 4% increase in clock speed results in approximately a 20% increase in overall performance.
The SPARC64 VII+ is socket compatible with its predecessor, the SPARC64 VII. Existing high-end M-class servers are able to upgrade to the SPARC64 VII+ processors in the field.
The SPARC64 VIIIfx, code-named Venus, is an eight-core version of the SPARC64 VII. It includes a memory controller and 760 million transistors. The processor is capable of 128 GFLOPS and is fabricated using Fujitsu's 45 nm process technology.
- Registers: 192 integer, 256 floating point; 8 FP ops, or 4 FMA ops, per cycle; 3 interrupt.
- Address range: 41-bit (up to 1FFFFF00000h).
- Translation lookaside buffer: 16 fetch + 256 4-way store instruction, 512 4-way store data, no victim cache
- Page sizes: 8 KB, 64 KB, 512 KB, 4 MB, 32 KMB, 256 MB, 2 KGB
- Translation storage buffer: Not supported in hardware
- SIMD: max 2 parallel calculations, supports max 8 floating point values per cycle. Double-precision floating-point register can be used for fixed-point calculations. Operands can be single- or double-precision floating-point values.
More on specifications and architecture is in this Fujitsu presentation.
The K computer is a supercomputer manufactured by Fujitsu and located at the RIKEN Advanced Institute for Computational Science campus in Kobe, Japan. It uses 8-core SPARC64 VIIIfx processors. In June 2011, TOP500 Project Committee announced that the K Computer topped the LINPACK benchmark with the performance of 8.162 petaflops with a computing efficiency ratio of 93.0%, making it the fastest supercomputer in the world at that time.
Fujitsu introduced the SPARC64 IXfx processor in November 2011 when they revealed the PRIMEHPC FX10 supercomputer architecture. The IXfx processor has 16 cores, 12 MB shared L2 cache, runs at 1.85 GHz, will reach a peak performance of 236.5 GFLOPS and will have a power efficiency of more than 2 GFLOPS per watt, i.e. 115 W per chip. It uses a SPARC v9 ISA, extended for high performance computing, with increased amounts of registers for integer and floating point computing.
Fujitsu introduced the SPARC64 XIfx processor in August 2014 at the Hot Chips symposium. The XIfx processor has 32 cores and 2 assistant cores organized into two Core Memory Groups with 12 MB shared L2 cache each for a total of 24 MB. It runs at 2.2 GHz, has a peak performance of 1.1 TFLOPS. Compared to the Sparc64 IXfx it will offer an improvement of 3.2 for double precision and 6.1 for single precision. The L1 cache has a throughput of 4.4 Tbytes per second. It uses Hybrid Memory Cube which has memory modules stacked on top of each other for an increased throughput of 30 Gbytes per second. The SIMD units are 256 Bit wide. The Sparc64 XIfx will be produced in a 20 nm process with 3.75 billion transistors. The XIfx uses the Tofu 2 interconnect with a maximum speed of 12.5 Gbytes per second. Twelve XIfx chips will fit into a 2U chassis. Servers with the chip will also support optical interfaces. A 100 Petaflops system could be build in a similar setup like the PRIMEHPC FX10.
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