|Max. CPU clock rate||2.85 GHz to 3.0 GHz|
|Min. feature size||40 nm|
|Instruction set||SPARC V9|
|L1 cache||8×16+16 kB|
|L2 cache||8×128 kB|
|L3 cache||4 MB|
The SPARC T4 is a SPARC multicore microprocessor introduced in 2011 by Oracle Corporation. The processor is designed to offer high multithreaded performance (8 threads per core of which 2 can be executed simultaneously, 8 cores per chip), as well as high single threaded performance from the same chip. The chip is the first Sun/Oracle SPARC chip to use out-of-order integer execution units, and also incorporates one floating point unit and one dedicated cryptographic unit per core. The cores use the 64-bit SPARC version 9 architecture running at frequencies between 2.85 and 3.0 GHz, and are built at a 40 nm process size with total chip die size of 403 mm2 (0.625 sq in).
History and design
An eight core, eight thread per core chip built at a 40 nm process and running at 2.5 GHz was described in Sun Microsystems' processor roadmap of 2009, codenamed Yosemite Falls, given an expected release date of late 2011, and was expected to introduce a new microarchitecture, codenamed "VT Core"; the online technology website The Register speculated that this chip would be named "T4", being the successor to the SPARC T3. The Yosemite Falls CPU product remained on Oracle Corporation's processor roadmap after the company took over Sun in early 2010. In December 2010 the T4 processor was confirmed by Oracle's VP of hardware development to be designed for improved per-thread performance, with eight cores, with an expected release within one year.
The processor design was presented at the 2011 Hot Chips conference; the cores (renamed "S3" from "VT") included a dual issue 16 stage integer pipeline, and 11-cycle floating point pipeline, both giving improvements over the previous ("S2") core used in the SPARC T3 processor. Each core had associated 16 kB data and 16 kB instruction L1 caches, and 128 kB L2 Cache. Cores also include a thread priority mechanism (called "critical thread API") whereby one thread gains preferential access to a core's hardware, giving increased performance. Cryptographic performance was also increased over the T3 chip by design improvements including a new set of cryptographic instructions. All eight cores share 4 MB L3 cache. Total transistor count was approximately 855 million. The design is the first Sun/Oracle SPARC processor with out-of-order execution. Initial product releases of a single T4 processor rack server ran at 2.85 GHz, and processor speeds of up to 3 GHz were achieved on the early systems.
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- Matthew Finnegan, "Oracle lords it over HP and IBM with SPARC T4", news.techeye.net (TechEye)