Serial Presence Detect

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Serial Presence Detect (SPD) refers to a standardized way to automatically access information about a computer memory module. Earlier 72-pin SIMMs included 5 pins which provided 5 bits of Parallel Presence Detect (PPD) data, but the 168-pin DIMM standard changed to a serial presence detect to encode much more information.^[1]

When an ordinary modern computer is turned on, it starts by doing a self-test (POST). Since about the mid-1990s, this process includes automatically configuring the hardware currently present. SPD is a memory hardware feature that makes it possible for the computer to know what memory is present, and what timings to use to access the memory.

Some computers adapt to hardware changes completely automatically. In most cases, there is a special optional procedure for accessing BIOS parameters, to view and potentially make changes in settings. It may be possible to control how the computer uses the memory SPD data -- to choose which settings to use, to selectively modify the memory timings, or possibly to completely over-ride the SPD data (see over-clocking).

Contents 1 Stored information 2 Extensions 2.1 Enhanced Performance Profiles (EPP) 2.2 Extreme Memory Profile (XMP) 2.3 Vendor-specific memory 3 Reading and writing SPD information 4 On older equipment 5 References 6 External links

[edit] Stored information

In order for a memory module to support SPD, the JEDEC standards require certain parameters to be placed in the lower 128 bytes of an EEPROM located on the memory module. These bytes contain timing parameters, manufacturer, serial number and other useful information about the module. This data allows a device utilizing the memory to automatically determine key parameters of the module. For example, the SPD data on an SDRAM module might provide information about the CAS latency, allowing this to be correctly set without user intervention.

The SPD EEPROM is accessed using SMBus, a variant of the I²C protocol. This reduces the number of communication pins on the module to just two: a clock signal and a data signal. The EEPROM shares ground pins with the RAM, has its own power pin, and has three additional pins (SA0–2) to identify the slot, which are used to assign the EEPROM a unique address in the range 0x50–0x57. Not only can the communication lines be shared among 8 memory modules, the same SMBus is commonly used on motherboards for system health monitoring tasks such as reading power supply voltages, CPU temperatures, and fan speeds.

(SPD EEPROMs also respond to I²C addresses 0x30–0x37 if they have not been write protected, and an extension uses addresses 0x18–0x1F to access an optional on-chip temperature sensor.^[2])

SPD defines three DRAM timings: highest CAS latency (fastest clock), and two lower CAS latencties (progressively lower clock speeds).

SPD contents for DDR SDRAM^[3]

Byte	b7	b6	b5	b4	b3	b2	b1	b0	Notes
0	Number of bytes written								Typically 128
1	log2(Size of SPD EEPROM)								Typically 8 (256 bytes)
2	Basic memory type (7 = DDR SDRAM)
3	Bank 2 row address bits (0–15)				Bank 1 row address bits (1–15)				Bank 2 is 0 if same as bank 1.
4	Bank 2 column address bits (0–15)				Bank 1 column address bits (1–15)				Bank 2 is 0 if same as bank 1.
5	Number of RAM banks on module (1–255)								Commonly 1 or 2
6	Module data width low byte								Commonly 64, or 72 for ECC DIMMs
7	Module data width high byte								Zero unless width ≥ 256 bits
8	Voltage Interface Level of this assembly (not the same as Vcc supply voltage) (0–5)								Decoded by table lookup
9	Nanoseconds (0–15)				Tenths of nanoseconds (0.0–0.9)				Clock cycle time at highest CAS latency.
10	Tenths of nanoseconds (0.0–0.9)				Hundredths of nanoseconds (0.00–0.09)				SDRAM access time from clock (tAC)
11	DIMM configuration type (0–2) non-ECC/parity/ECC								Table lookup
12	Self	Refresh period (0–5) 64/256/128/32/16/8 kHz							Refresh requirements
13	Bank 2 2x	Bank 1 Primary SDRAM width (1–127)							Width of bank 1 data SDRAM devices. Bank 2 may be same width, or 2x width if bit 7 is set.
14	Bank 2 2x	Bank 1 ECC SDRAM width (0–127)							Width of bank 1 ECC/parity SDRAM devices. Bank 2 may be same width, or 2x width if bit 7 is set.
15	Clock delay for random column reads								Typically 1
16	Page	—	—	—	8	4	2	1	Burst lengths supported (bitmap)
17	Banks per SDRAM device (1–255)								Typically 4
18	—	4	3.5	3	2.5	2	1.5	1	CAS latencies supported (bitmap)
19	—	6	5	4	3	2	1	0	CS latencies supported (bitmap)
20	—	6	5	4	3	2	1	0	WE latencies supported (bitmap)
21	—	x	Diff clock	FET switch external enable	FET switch on-board enable	On-card PLL	Registered	Buffered	Memory module feature bitmap
22	Fast AP	Concurrent auto precharge	Upper Vcc(supply voltage) tolerance	Lower Vcc(supply voltage) tolerance	—	—	—	Includes weak driver	Memory chip feature bitmap
23	Nanoseconds (0–15)				Tenths of nanoseconds (0.0–0.9)				Clock cycle time at medium CAS latency.
24	Tenths of nanoseconds (0.0–0.9)				Hundredths of nanoseconds (0.00–0.09)				Data access time from clock (tAC)
25	Nanoseconds (0–15)				Tenths of nanoseconds (0.0–0.9)				Clock cycle time at short CAS latency.
26	Tenths of nanoseconds (0.0–0.9)				Hundredths of nanoseconds (0.00–0.09)				Data access time from clock (tAC)
27	Nanoseconds (1–63)						1/4 ns (0–0.75)		Minimum row precharge time (tRP)
28	Nanoseconds (1–63)						1/4 ns (0–0.75)		Minimum row active–row active delay (tRRD)
29	Nanoseconds (1–63)						1/4 ns (0–0.75)		Minimum RAS to CAS delay (tRCD)
30	Nanoseconds (1–255)								Minimum active to precharge time (tRAS)
31	512 MiB	256 MiB	128 MiB	64 MiB	32 MiB	16 MiB/ 4 GiB	8 MiB/ 2 GiB	4 MiB/ 1 GiB	Module bank density (bitmap). Two bits set if different size banks.
32	Tenths of nanoseconds (0.0–0.9)				Hundredths of nanoseconds (0.00–0.09)				Address/command setup time from clock
33	Tenths of nanoseconds (0.0–0.9)				Hundredths of nanoseconds (0.00–0.09)				Address/command hold time after clock
34	Tenths of nanoseconds (0.0–0.9)				Hundredths of nanoseconds (0.00–0.09)				Data input setup time from clock
35	Tenths of nanoseconds (0.0–0.9)				Hundredths of nanoseconds (0.00–0.09)				Data input hold time after clock
35–40	reserved								Superset information
41	Nanoseconds (1–255)								Minimum active to active/refresh time (tRC)
42	Nanoseconds (1–255)								Minimum refresh to active/refresh time (tRFC)
43	Nanoseconds (1–63)						1/4 ns (0–0.75)		Maximum clock cycle time (tCK max) If all-ones, there is no maximum.
44	Hundredths of nanoseconds (0.01–2.55)								Maximum skew, DQS to any DQ. (tDQSQ max)
45	Tenths of nanoseconds (0.0–1.2)				Hundredths of nanoseconds (0.00–0.09)				Read data hold skew factor (tQHS)
46	reserved								For futre standardization
47	—						Height		Height of DIMM module, table lookup
48–61	reserved								For future standardization
62	Major revision (0–9)				Minor revision (.0–.9)				SPD revision level, 0.0 or 1.0
63	Checksum								Sum of bytes 0–62, not negated
64–71	Manufacturer JEDEC ID								Stored little-endian, trailing zero-pad.
72	Module manufacturing location								Vendor-specific code
73–90	Module part number								ASCII, space-padded
91–92	Module revision code								Vendor-specific code
93	Tens of years (00–90)				years (0–9)				Manufacturing date (YYWW)
94	Tens of weeks (00–50)				weeks (0–9)
95–98	Module serial number								Vendor-specific code
99–127	Manufacturer-specific data								Could be enhanced performance profile

The DDR2 SPD standard makes a number of changes, but is roughly similar to the above. One useful thing it deletes is the confusing and little-used support DIMMS with two ranks of different sizes. For cycle time fields (bytes 9, 23, 25 and 49) which are encoded in BCD, some additional encodings are defined for the last digit to represent some common timings exactly:

Hex	Binary	Significance
A	1010	0.25
B	1011	0.33
C	1100	0.66
D	1101	0.75
E	1110	0.875 (nVidia XMP extension)
F	1111	Reserved, do not use

SPD contents for DDR2 SDRAM^[4]

Byte	b7	b6	b5	b4	b3	b2	b1	b0	Notes
0	Number of bytes written								Typically 128
1	log2(Size of SPD EEPROM)								Typically 8 (256 bytes)
2	Basic memory type (8 = DDR2 SDRAM)
3	Reserved, zero				Row address bits (1–15)
4	Reserved, zero				Column address bits (1–15)
5	Vertical height			Stack?	ConC?	Ranks−1 (1–8)			Commonly 0 or 1, meaning 1 or 2
6	Module data width								Commonly 64, or 72 for ECC DIMMs
7	Reserved, zero
8	Voltage Interface Level of this assembly (not the same as Vcc supply voltage) (0–5)								Decoded by table lookup Commonly 5 = SSTL 1.8V
9	Nanoseconds (0–15)				Tenths of nanoseconds (0.0–0.9)				Clock cycle time at highest CAS latency.
10	Tenths of nanoseconds (0.0–0.9)				Hundredths of nanoseconds (0.00–0.09)				SDRAM access time from clock (tAC)
11	DIMM configuration type (0–2) non-ECC/parity/ECC								Table lookup
12	Self	Refresh period (0–5) 64/256/128/32/16/8 kHz							Refresh requirements
13	Primary SDRAM width (1–255)								Commonly 8 (module built from x8 parts) or 16
14	ECC SDRAM width (0–255)								Width of bank ECC/parity SDRAM devices. Commonly 0 or 8.
15	Reserved, zero
16	—	—	—	—	8	4	—	—	Burst lengths supported (bitmap)
17	Banks per SDRAM device (1–255)								Typically 4 or 8
18	—	—	5	4	3	2	—	—	CAS latencies supported (bitmap)
19	Reserved, zero
20	—	—	Mini-UDIMM	Mini-RDIMM	Micro-DIMM	SO-DIMM	UDIMM	RDIMM	DIMM type of this assembly (bitmap)
21	—	Anal. probe	—	FET switch external enable	—	—	—	—	Memory module feature bitmap
22	—	—	—	—	—	—	—	Includes weak driver	Memory chip feature bitmap
23	Nanoseconds (0–15)				Tenths of nanoseconds (0.0–0.9)				Clock cycle time at medium CAS latency.
24	Tenths of nanoseconds (0.0–0.9)				Hundredths of nanoseconds (0.00–0.09)				Data access time from clock (tAC)
25	Nanoseconds (0–15)				Tenths of nanoseconds (0.0–0.9)				Clock cycle time at short CAS latency.
26	Tenths of nanoseconds (0.0–0.9)				Hundredths of nanoseconds (0.00–0.09)				Data access time from clock (tAC)
27	Nanoseconds (1–63)						1/4 ns (0–0.75)		Minimum row precharge time (tRP)
28	Nanoseconds (1–63)						1/4 ns (0–0.75)		Minimum row active–row active delay (tRRD)
29	Nanoseconds (1–63)						1/4 ns (0–0.75)		Minimum RAS to CAS delay (tRCD)
30	Nanoseconds (1–255)								Minimum active to precharge time (tRAS)
31	512 MiB	256 MiB	128 MiB	16 GiB	8 GiB	4 GiB	2 GiB	1 GiB	Size of each rank (bitmap).
32	Tenths of nanoseconds (0.0–1.2)				Hundredths of nanoseconds (0.00–0.09)				Address/command setup time from clock
33	Tenths of nanoseconds (0.0–1.2)				Hundredths of nanoseconds (0.00–0.09)				Address/command hold time after clock
34	Tenths of nanoseconds (0.0–0.9)				Hundredths of nanoseconds (0.00–0.09)				Data input setup time from strobe
35	Tenths of nanoseconds (0.0–0.9)				Hundredths of nanoseconds (0.00–0.09)				Data input hold time after strobe
36	Nanoseconds (1–63)						1/4 ns (0–0.75)		Minimum write recovery time (tWR)
37	Nanoseconds (1–63)						1/4 ns (0–0.75)		Internal write to read command delay (tWTR)
38	Nanoseconds (1–63)						1/4 ns (0–0.75)		Internal read to precharge command delay (tRTP)
39	Reserved, zero								Reserved for "memory analysis probe characteristics"
40	—	tRC fractional ns (0–5) 0/0.25/0.33/0.5/0.66/0.75			tRFC fractional ns (0–5) 0/0.25/0.33/0.5/0.66/0.75			tRFC +256 ns	Extension of bytes 41 and 42.
41	Nanoseconds (1–255)								Minimum active to active/refresh time (tRC)
42	Nanoseconds (1–255)								Minimum refresh to active/refresh time (tRFC)
43	Nanoseconds (0–15)				Tenths of nanoseconds (0.0–0.9)				Maximum clock cycle time (tCK max)
44	Hundredths of nanoseconds (0.01–2.55)								Maximum skew, DQS to any DQ. (tDQSQ max)
45	Tenths of nanoseconds (0.0–1.2)				Hundredths of nanoseconds (0.00–0.09)				Read data hold skew factor (tQHS)
46	Microseconds (1–255)								PLL relock time
47–61	reserved								For future standardization.
62	Major revision (0–9)				Minor revision (.0–.9)				SPD revision level, usually 1.0
63	Checksum								Sum of bytes 0–62, not negated
64–71	Manufacturer JEDEC ID								Stored little-endian, trailing zero-pad.
72	Module manufacturing location								Vendor-specific code
73–90	Module part number								ASCII, space-padded (Limited to (,-,),A-Z,a-z,0-9,space)
91–92	Module revision code								Vendor-specific code
93	Years since 2000 (0–255)								Manufacturing date (YYWW)
94	Weeks (1–52)
95–98	Module serial number								Vendor-specific code
99–127	Manufacturer-specific data								Could be enhanced performance profile

[edit] Extensions

The JEDEC standard only specifies some of the SPD bytes. The truly critical data fits into the first 64 bytes,^{[5][6][3][4][7]} while the some of the remainder is earmarked for manufacturer identification. However, a 256-byte EEPROM is generally provided. A number of uses have been made of the remaining space.

[edit] Enhanced Performance Profiles (EPP)

Memory generally comes with conservative timing recommendations in the SPD ROM, to ensure basic functionality on all systems. Enthusiasts often spend considerable time manually adjusting the memory timings for higher speed.

Enhanced Performance Profiles is an extension of SPD, developed by NVIDIA and Corsair, which includes additional information for higher-performance operation of DDR2 SDRAM, including supply voltages and command timing information not included in the JEDEC SPD spec. The EPP information is stored in the same EEPROM, but in bytes 99-127 which are unused by standard DDR2 SPD.^[8]

EPP SPD ROM usage

Bytes	Size	Full profiles	Abbreviated profiles
99–103	5	EPP header
104–109	6	Profile FP1	Profile AP1
110–115	6		Profile AP2
116–121	6	Profile FP2	Profile AP3
122–127	6		Profile AP4

The parameters are particularly designed to fit the memory controller on the nForce 5, nForce 6 and nForce 7 chipsets. NVIDIA encourages support for EPP in the BIOS for its high-end motherboard chipsets. This is intended to provide "one-click overclocking" to get better performance with minimal effort.

NVIDIA's name for EPP memory that has been qualified for performance and stability is "SLI-ready memory".^[9]. The term "SLI-ready-memory" has caused some confusion, as it has nothing to do with SLI video. One can use EPP/SLI memory with a single video card (even a non-NVIDIA card), and one can run a multi-card SLI video setup without EPP/SLI memory.

An extended version, EPP 2.0, supports DDR3 memory as well.^[10]

[edit] Extreme Memory Profile (XMP)

A similar, Intel-developed JEDEC SPD extension for DDR3 SDRAM DIMMs. This uses bytes 176–255, which are unallocated by JEDEC, to encode higher-performance memory timings.^[11]

XMP SPD ROM usage

Bytes	Size	Use
176–185	10	XMP header
186–218	33	XMP profile 1
219–254	36	XMP profile 2

[edit] Vendor-specific memory

A very common (mis-)use is the writing of information to certain memory regions in order to bind vendor-specific memory modules to a specific system. One vendor known to do this is Fujitsu-Siemens Computers. Adding different memory module to the system usually results in a refusal or other counter-measures (like pressing F1 on every boot, very problematic for a server which usually reboots without user intervention).

02 0E 00 01-00 00 00 EF-02 03 19 4D-BC 47 C3 46 ...........M.G.F
53 43 00 04-EF 4F 8D 1F-00 01 70 00-01 03 C1 CF SC...O....p.....

This is the output of a 512MB memory module from Micron Technologies, branded for Fujitsu-Siemens Computers, note the "FSC" string. Memory modules which do not have this information starting at offset 128h will be refused by the BIOS of the system.

[edit] Reading and writing SPD information

Memory module manufacturers write the SPD information to the eeprom on the module. Motherboard BIOSes read the SPD information to configure the memory controller. There exist several programs that are able to read and modify SPD information on most, but not all motherboard chipsets.

• dmidecode program can decode information about memory (and other things) and runs on Linux, FreeBSD, NetBSD, OpenBSD, BeOS, Cygwin and Solaris.

• On Linux systems, the user space program decode-dimms.pl^[12] provided with lm_sensors ^[13] decodes and prints information on any memory with SPD information in the computer. On more recent Linux distributions, decode-dimms is available as part of i2c-tools.

• OpenBSD has included a driver (spdmem(4)) since version 4.3 to provide information about memory modules. The driver was ported from NetBSD, where it will be available in release 5.0.

• coreboot reads and uses SPD information to initialize all memory controllers in a computer with timing, size and other properties.

• On Windows systems, there are programs like AIDA32, CPU-Z, SIW, PCWizard 2007 and SPDTool that are able to display and modify SPD information.

Chipset independent reading and writing of SPD information is done by accessing the memory`s eeprom directly with eeprom programmer hard- and software.

[edit] On older equipment

This section may stray from the topic of the article into the topic of another article, Parallel Presence Detect. Please help improve this section or discuss this issue on the talk page.

Some older equipment require the use of SIMMs with SPD (more commonly called simply presence detect or PD). Some of this equipment uses non-standard PD coding; IBM computers and Hewlett-Packard LaserJet and other printers in particular. While old computers are rarely found, many old Laserjet printers are in use. Discontinued HP memory modules are officially recommended, but any 72-pin SIMM module within the capacity range supported by the printer and with the correct PD code should work. All printers will work with FPM (Fast Page Mode) memory; it is reported that some, but not all, will work with EDO memory^[14]. It is fairly easy to solder wires to the PD pins to make non-HP modules work^[15]. HP printers of this type specify that RAM not faster than 70ns be used; this is probably due to a limitation of the PD encoding. Faster RAM can be used, but the PD encoding should indicate a speed of 70ns.

[edit] References

1. ^ Thomas P. Koenig; Nathan John (1997-02-03), "Serial Presence Detection poised for limelight", Electronic News 43 (2153), http://findarticles.com/p/articles/mi_m0EKF/is_n2153_v43/ai_19102210/ 
2. ^ JEDEC Standard 21-C section 4.1.4 "Definition of the TSE2002av Serial Presence Detect (SPD) EEPROM with Temeprature Sensor (TS) for Memory Module Applications"
3. ^ ^{a b} JEDEC Standard 21-C section 4.1.2.4 "SPDs for DDR SDRAM"
4. ^ ^{a b} JEDEC Standard 21-C section 4.1.2.10 "Specific SPDs for DDR2 SDRAM"
5. ^ JEDEC Standard 21-C section 4.1.2 "SERIAL PRESENCE DETECT STANDARD, General Standard"
6. ^ JEDEC Standard 21-C section 4.1.2.5 "Specific PDs for Synchronous DRAM (SDRAM)"
7. ^ JEDEC Standard 21-C section 4.1.2.11 "Serial Presence Detect (SPD) for DDR3 SDRAM Modules"
8. ^ DDR2 UDIMM Enhanced Performance Profiles Design Specification, NVIDIA, 2006-05-12, http://www.nvidia.com/content/epp/epp_specifications.pdf, retrieved on 2009-05-05 
9. ^ http://www.nvidia.com/docs/CP/45121/sli_memory.pdf
10. ^ Enhanced Performance Profiles 2.0 (pages 2–3)
11. ^ Intel® Extreme Memory Profile (Intel XMP) DDR3 Technology
12. ^ http://www.lm-sensors.org/browser/i2c-tools/trunk/eeprom/decode-dimms decode-dimms.pl Perl program
13. ^ http://www.lm-sensors.org/
14. ^ Page on memory upgrades for HP printers
15. ^ Making Standard SIMMs Work – Memory Upgrade on the HP LaserJet 6MP/5MP

[edit] External links

• Serial Presence Detect Standard, General Standard
• SPD Rev1.0 for DDR SDRAM
• SPD Rev1.2 for DDR2 SDRAM
• Linux package i2c-tools
• Instructions on how to use lm-sensors or i2c-tools to read the data: http://ornellas.apanela.com/dokuwiki/pub:spd