|L1 cache||128 KB|
|L2 cache||512 KB|
|L3 cache||12 MB|
Skylake will come in four variants, namely Skylake-S (SKL-S), Skylake H (SKL-H), Skylake U (SKL-U), and Skylake Y (SKL-Y). The H, U and Y variants will be manufactured in ball grid array (BGA) packaging, while the S variant will be manufactured in land grid array (LGA) packaging. An important redesign in Skylake will be that the fully integrated voltage regulator (FIVR), which was introduced with Haswell processors, will be abandoned and no longer included on the die.
The Platform Controller Hub (PCH) will be integrated onto the die for Skylake's H, U and Y variants, effectively following a system-on-chip (SoC) design layout, while the S variant will remain as a two-chip design. On the variants which will use the PCH, Direct Media Interface (DMI) 2.0 will be replaced by DMI 3.0, which promises speeds of up to 8 GT/s. Variants U and Y will support one DIMM slot per channel, while variants H and S will support two DIMM slots per channel. All processors at the time of release will have their clock multipliers locked.
- 14 nm manufacturing process
- 3.5 billion transistor without integrated graphic unit.
- LGA 1151 socket
- Z170/H170 chipset (Sunrise Point)
- Thermal design power (TDP) up to 95 W (LGA 1151)
- Support for both DDR3 SDRAM and DDR4 SDRAM in mainstream variants, with up to 64 GB of RAM on LGA 1151 variants.
- Support for 20 PCI Express 3.0 lanes (LGA 1151)
- Support for PCI Express 4.0 (Skylake-E/EP/EX)
- Support for Thunderbolt 3.0 (Alpine Ridge)
- 128 KB L1 cache (64 KB 16-way set associative instruction cache + 64 KB 16-way set associative data cache; two cycles)
- 512 KB L2 cache, 16-way set associative (six cycles)
- 12 MB L3 cache, 24-way set associative (12 cycles)
- 64 to 128 MB L4 eDRAM cache on certain SKUs.
- Up to four cores as the default mainstream configuration
- Support for SATA Express
- AVX-512F: Advanced Vector Extensions 3.2
- Support x86-64e which integer register increased from 16 in x64 standard to 32 in EM64T enhanced mode (r16–r31 for enhanced mode only, while it can be used for memory segment in normal x64 ISA)
- instruction decoder increase from 4 (since core 2) to 6 in skylake and stage pipeline are also increase to 6 issue.
- Intel SHA Extensions: SHA-1 and SHA-256 (Secure Hash Algorithms)
- Intel MPX (Memory Protection Extensions)
- Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
- Skylake's integrated GPU supports Direct3D 12 at feature level 12_0 
Multiple combinations of integrated L4 eDRAM cache will be available with various Skylake configurations. Some of the available models will have configurable thermal design power (cTDP); for example, Skylake-S (SKL-S) processors will be available in two TDP variants, one around 35 W and the other around 65 W. Skylake-S processors will also have support for both DDR3 and DDR4 SDRAM.
|SKL-Y-1||2||GT2||LPDDR3 1600 MHz||N/A||4 W|
|SKL-U-1||2||GT2||LPDDR3 1600 MHz||N/A||15 W|
|SKL-U-2||2||GT3e||LPDDR3 1600 MHz||64 MB||28 W|
|SKL-H-1||4||GT2||DDR4 2133 MHz||N/A||35 W|
|SKL-H-2||4||GT4e||DDR4 2133 MHz||128 MB||45 W|
|SKL-S-1||2||GT2||DDR4 2133 MHz or DDR3L/DDR3L-RS 1600 MHz||N/A||35–65 W|
|SKL-S-2||4||GT2||DDR4 2133 MHz or DDR3L/DDR3L-RS 1600 MHz||N/A||95 W|
|SKL-S-3||4||GT4e||DDR4 2133 MHz or DDR3L/DDR3L-RS 1600 MHz||64 MB||35–65 W|
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