Soft microprocessor
From Wikipedia, the free encyclopedia
(Redirected from
Soft processor)
A soft microprocessor (also called softcore microprocessor or a soft processor) is a microprocessor core that can be wholly implemented using logic synthesis. It can be implemented via different semiconductor devices containing programmable logic (e.g., ASIC, FPGA, CPLD), including both high-end and commodity variations[1].
Most systems, if they use a soft processor at all, only use a single soft processor. However, a few designers tile as many soft cores onto an FPGA as will fit.[2] In those multi-core systems, rarely used resources can be shared between all the cores in a cluster, leading to Jan's Razor.
Jan's Razor: In a chip multiprocessor design, strive to leave out all but the minimal kernel set of features from each processing element, so as to maximize processing elements per die.
[3]
—Jan Gray
While many people put exactly one soft microprocessor on a FPGA, a sufficiently large FPGA can hold two or more soft microprocessors, resulting in a multi-core processor. The number of soft processors on a single FPGA is only limited by the size of the FPGA.[4] Some people have put dozens or hundreds of soft microprocessors on a single FPGA.[5][6][7][8][9]
[edit] Core comparison
| Processor |
Developer |
Open Source |
Bus Support |
Notes |
Project Home |
| TSK3000A |
Altium |
No Royalty-Free |
Wishbone |
32-bit R3000 style RISC Modified Harvard Architecture CPU |
Embedded Design on Altium Wiki |
| TSK51/52 |
Altium |
No Royalty-Free |
Wishbone / Intel 8051 |
8-bit Intel 8051 instruction set compatible, lower clock cycle alternative |
Embedded Design on Altium Wiki |
| OpenSPARC T1 |
Sun |
Yes |
|
64-bit |
OpenSPARC.net |
| MicroBlaze |
Xilinx |
No |
PLB, OPB, FSL, LMB, AXI4 |
|
Xilinx MicroBlaze |
| PicoBlaze |
Xilinx |
Yes |
|
|
Xilinx PicoBlaze |
| Nios, Nios II |
Altera |
No |
Avalon |
|
Altera Nios II |
| Cortex-M1 |
ARM |
No |
|
|
[6] |
| eSi-RISC |
EnSilica |
No |
AMBA AXI, AHB and APB |
Configurable as 16 or 32-bit. Supports ASIC and FPGA. |
EnSilica eSi-RISC |
| LatticeMico32 |
Lattice |
Yes |
Wishbone |
|
LatticeMico32 |
| LEON2(-FT) |
ESA |
Yes |
AMBA2 |
SPARC V8 |
ESA |
| LEON3/4 |
Aeroflex Gaisler |
Yes |
AMBA2 |
SPARC V8 |
Aeroflex Gaisler |
| Navré |
Sébastien Bourdeauducq |
Yes |
Direct SRAM |
Atmel AVR compatible 8-bit RISC |
Project page at Opencores |
| OpenRISC |
OpenCores |
Yes |
Wishbone |
32-bit; Done in ASIC, Actel, Altera, Xilinx FPGA |
OR1K |
| pAVR |
Doru Cuturela |
Yes |
|
Atmel AVR compatible 8-bit RISC |
Project page at Opencores |
| AEMB |
Shawn Tan |
Yes |
Wishbone |
MicroBlaze EDK 3.2 compatible Verilog core |
AEMB |
| OpenFire |
Virginia Tech CCM Lab |
Yes |
OPB, FSL |
Binary compatible with the MicroBlaze |
[7] [10] |
| SecretBlaze |
Lyonel Barthe |
Yes |
Wishbone |
MicroBlaze ISA, VHDL |
SecretBlaze |
| SYNPIC12 |
Miguel Angel Ajo Pelayo |
Yes MIT |
|
PIC12F compatible, program synthesised in gates |
nbee.es |
| PacoBlaze |
Pablo Bleyer |
Yes |
|
Compatible with the PicoBlaze processors |
PacoBlaze |
| CPU86 |
HT-Lab |
Yes |
|
8088 compatible CPU in VHDL |
cpu86 |
| xr16 |
Jan Gray |
No |
XSOC abstract bus |
16-bit RISC CPU + SoC featured in Circuit Cellar Magazine #116-118 |
XSOC/xr16 |
| JOP |
Martin Schoeberl |
Yes |
SimpCon / Wishbone (extension) |
Stack oriented, hard real-time support, executes Java bytecode directly |
Jop |
| ERIC5 |
Entner Electronics |
No |
|
9-bit RISC, very small size, C-programmable |
ERIC5 |
| YASEP |
Yann Guidon |
Yes AGPLv3 |
Direct SRAM |
16 or 32 bits, VHDL & JavaScript, not ready, sort of anti-F-CPU |
yasep.org (Firefox required) |
| Zet |
Zeus Gómez Marmolejo |
Yes |
Wishbone |
x86 PC clone |
Zet |
| ZPU |
Zylin AS |
Yes |
Wishbone |
Stack based CPU, configurable 16/32 bit datapath, eCos support |
Zylin CPU |
[edit] See also
[edit] References
[edit] External links