Special function register

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A Special Function Register (or Special Purpose Register, or simply Special Register) is a register within a microprocessor, which controls or monitors various aspects of the microprocessor's function. Depending on the processor architecture, this can include, but is not limited to:

  • I/O and peripheral control (such as serial ports or general-purpose IOs)
  • timers
  • stack pointer
  • stack limit (to prevent overflows)
  • program counter
  • subroutine return address
  • processor status (servicing an interrupt, running in protected mode, etc.)
  • condition codes (result of previous comparisons)

Because special registers are closely tied to some special function or status of the processor, they might not be directly writeable by normal instructions (such as adds, moves, etc.). Instead, some special registers in some processor architectures require special instructions to modify them. For example, the program counter is not directly writeable in many processor architectures. Instead, the programmer uses instructions such as return from subroutine, jump, or branch to modify the program counter. For example, the condition code register might not directly writable, instead being updated only by compare instructions.

Intel Processors[edit]

Some of SFR bits may be set directly using SETB/LDB instructions on proper address, whereas others may require usage of specific instructions. The Intel 80196 class microcontroller has 24 SFRs, each 1 Byte in size; standard Intel 8051 chips have 21 SFRs.

The Special Function Register (SFR) is the upper area of addressable memory, from address 0x80 to 0xFF. This area of memory cannot be used for data or program storage, but is instead a series of memory-mapped ports and registers. All port input and output can therefore be performed by memory move operations on specified addresses in the SFR. Also, different status registers are mapped into the SFR, for use in checking the status of the 8051, and changing some operational parameters of the 8051.

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