Specman is an EDA tool that provides advanced automated Functional verification of hardware designs. It provides an environment for working with, compiling, and debugging testbench environments written in the e Hardware Verification Language. Specman also offers automated testbench generation to boost productivity in the context of block, chip, and system verification.
The Specman tool itself does not include an HDL-simulation environment (such as VHDL or Verilog.) To simulate an e-testbench with a design written in VHDL/Verilog, Specman must be run in conjunction with a separate HDL simulation tool. In principle, Specman can co-simulate with any HDL-simulator supporting standard PLI or VHPI interface, such as Cadence's NC-Sim or Verilog-XL, Synopsys's VCS, or Mentor's ModelSim, or Aldec's Riviera-PRO. But in practice, Specman is used almost exclusively with NC-Sim, where tighter product integration with NC-Sim offers both faster runtime performance and debug capabilities not available with other HDL-simulators.
It is now part of the Cadence's functional verification suite, "Incisive Enterprise Simulator", although Specman can still be licensed as a standalone product.
You can find related articles in
- The e language blog (Team Specman)
- Editor Syntax Highlighting Modes
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