System Management Mode

x86 processor modes
Mode	First supported
Real mode	Intel 8086
8080 emulation mode	NEC V20/V30 only
Protected mode	Intel 80286
Virtual 8086 mode	Intel 80386
Unreal mode	Intel 80386
System Management Mode	Intel 386SL
Long mode	AMD Opteron
Hardware virtualization	AMD Athlon 64, varies

System Management Mode (SMM) is an operating mode in which all normal execution (including the operating system) is suspended, and special separate software (usually firmware or a hardware-assisted debugger) is executed in high-privilege mode. It was first released with the Intel 386SL. While initially special SL versions were required for SMM, Intel incorporated SMM in its mainline 486 and Pentium processors in 1993. AMD copied Intel's SMM with the Enhanced Am486 processors in 1994. It is available in all later microprocessors in the x86 architecture.

Usage

Some uses of SMM are:

• Handle system events like memory or chipset errors.
• Manage system safety functions, such as shutdown on high CPU temperature and turning the fans on and off.
• Security functions, such as flash device lock down require SMM support on some chipsets.
• Deeper sleep power management support on Intel systems.
• Control power management operations, such as managing the voltage regulator modules.
• Emulate motherboard hardware that is unimplemented or buggy.
• Emulate a PS/2 mouse or keyboard by converting the messages from USB versions of those peripherals to the messages that would have been generated had PS/2 versions of such hardware been connected.
• Centralize system configuration, such as on Toshiba and IBM notebook computers.
• Hackers can break into SMM to run high-privileged rootkits as shown at Black Hat 2008.
• Emulate or forward calls to a Trusted Platform Module (TPM).

Entering SMM

SMM is entered via the SMI (system management interrupt), which is caused by:

• Motherboard hardware or chipset signaling via a designated pin SMI# of the processor chip. This signal can be an independent event.
• Software SMI triggered by the system software via an I/O access to a location considered special by the motherboard logic (port 0B2h is common).
• An IO write to a location which the firmware has requested that the processor chip act on.

Problems

• By design, the operating system cannot override or disable the SMI.
• Since the SMM code (SMI handler) is installed by the system firmware (BIOS), the OS and the SMM code may have expectations about hardware settings that are incompatible, such as different ideas of how the Advanced Programmable Interrupt Controller (APIC) should be set up.
• Operations in SMM take CPU time away from the OS, since the CPU state must be stored to memory (SMRAM) and any write-back caches must be flushed. This can destroy real-time behavior and cause clock ticks to get lost. The Windows and Linux kernels define an ‘SMI Timeout’ setting a period within which SMM handlers must return control to the operating system or it will ‘hang’ or ‘crash’.
• The SMM may disrupt the behavior of real-time applications with constrained timing requirements.
• A digital logic analyzer may be required to determine if the CPU has entered SMM (checking state of SMIACT# pin of CPU).
• Recovering the SMI handler code to analyze it for bugs, vulnerabilities and secrets requires a logic analyzer or disassembly of the system firmware.

See also

• MediaGX processor which implements nonexistent hardware via SMM
• Intel 80486SL
• Extensible Firmware Interface (EFI)
• Coreboot implements an open source SMM/SMI handler for some chipsets

External links

• Badness of SMM, part 1 and part 2
• Intel 32/64 Architectures Software Developer’s Manual Volume 3B: System Programming Guide, Part 2
• AMD Hammer BIOS and Kernel Developer's guide, Chapter 6
• An exploit against SMM based on OpenBSD
• SMM based rootkit
• SMM Rootkit limitations. (and how to defeat it)