|Headquarters||Santa Clara, California|
|Dennis Segers (CEO), Steve Teig (CTO)|
|Products||Three-dimensional integrated circuit (3-D FPGA)|
Number of employees
Tabula is a fabless semiconductor company based in Santa Clara, California. Founded in 2003 by Steve Teig (ex-CTO of Cadence), it has raised $215 million in venture funding. The company designs and builds three dimensional field programmable gate arrays (3-D FPGAs) and ranked third on the Wall Street Journal's annual "Next Big Thing" list in 2012.
Tabula develops ABAX, a family of three-dimensional integrated circuits. The company's field-programmable gate array (FPGA) chips are marketed as 3-D programmable logic devices or 3PLDs. The chips have 220-630 thousand 4-input lookup table (LUT) from the user point of view and are capable of working at 1.6 GHz physical clock speed. They also contain up to 1280 digital signal processing (DSP) blocks with 18x18 multipliers with pre-adder; up to 920 GPIO pins and 48 SerDes channels (up to 6.5 Gbit/s). ABAX are produced using 40 nm TSMC process and packaged in flip-chip packages with 1936 or 1156 pins.
Internally ABAX chips use high-frequency (1.6 GHz) reconfiguration between up to 8 config states, named folds, to emulate a high number of FPGA-resources. If all 8 folds are used to get maximum LUT capacity, user visible clock speed will be 200 MHz; for 4 folds capacity is halved but frequency is doubled and so on. Volume price of ABAX chips was planned in 2012 to be in the range of 100-200 USD.
There are also some network solutions by Tabula, like 100 or 40 Gb Ethernet to Interlaken bridges; high-speed packet search engines and multiport 10 gigabit ethernet processors (can be used as switch, router, or programmable NIC).
In February 2012 Tabula confirmed it will use 22-nm manufacturing process on Intel's Factories. At time of July 2013 only 5 companies were allowed to use Intel's manufacturing process: Achronix, Tabula, Netronome, Microsemi and Altera.
Spacetime is a product of Tabula that may go beyond the abilities of FPGAs. The company says that Spacetime represents two spatial dimensions and one time dimension as a unified 3D framework. According to Tabula, this appears to be a simplification that may deliver in production a new category of programmable devices (“3PLDs”) that may be denser, faster, and more capable than FPGAs yet still accompanied by software that automatically maps traditional RTL onto these novel fabrics.
- "Business is King Among ‘Next Big Thing’ Start-Ups". Venture Capital Dispatch. 27 September 2012. Retrieved 1 October 2012.
- Cromwell Schubarth (26 September 2012). "Here's 30 Bay Area startups pegged as 'Next Big Thing'". Business Journal. Retrieved 1 October 2012.
- Tom R. Halfhill (2010-03-29). "Tabula's Time Machine. Rapidly reconfigurable chips will challenge conventional FPGAs". Microprocessor Report #3 2010.
- Don Clark (2012-02-20). "Startup Tabula Turns to Intel As Manufacturing Partner". WSJ Blogs.
- Clive Maxfield (2012-02-21). "Tabula’s next-gen FPGAs to use Intel’s 22nm process featuring 3-D tri-gate transistors". EETimes.
- Intel dabbles in contract manufacturing, weighing tradeoffs // The Oregonian, July 27, 2013
- Official website
- Steve Teig Lecture on Tabula and Entrepreneurship to Stanford University Students, 2013.10.23
- Steve Teig Lecture on Spacetime 3D Programmable Integrated Circuits (11 min), 2012.06.18
- Steve Teig Lecture on Spacetime 3D Programmable Integrated Circuits (61 min), 2012.10.07