In computer science, a tagged architecture is a particular type of computer architecture where every word of memory constitutes a tagged union, being divided into a number of bits of data, and a tag section that describes the type of the data: how it is to be interpreted, and, if it is a reference, the type of the object that it points to.
Two notable series of tagged architectures were the Lisp machines, which had tagged pointer support at the hardware and opcode level, and the Burroughs large systems which had a data-driven tagged and descriptor-based architecture. Another "exemplary" instance was the architecture of the Rice Computer.
In addition to this, the original Xerox Smalltalk implementation used the least-significant bit of each 16-bit word as a tag bit: if it was clear then the hardware would accept it as an aligned memory address while if it was set it was treated as a (shifted) 15-bit integer. Current Intel documentation mentions that the lower bits of a memory address might be similarly used by some interpreter-based systems.
- The Memory Management Glossary: Tagged architecture
- Feustel, Edward A. (July 1973). "On the Advantages of Tagged Architecture" (PDF). IEEE Transactions on Computers: 644–656. Archived from the original on January 21, 2013. Retrieved January 21, 2013.
- Feustel, Edward A. (1972). "The Rice Research Computer -- A tagged architecture" (PDF). proceedings of the 1972 Spring Joint Computer Conference. American Federation of Information Processing Societies (AFIPS). pp. 369–377. Archived from the original on July 27, 2014. Retrieved July 27, 2014.
- Thornton, Adam. "A Brief History of the Rice Computer 1959-1971". Retrieved January 31, 2013. (mostly written in [or before] 1994, and archived by the Wayback Machine on a date indicated [by "20080224"] in the URL)
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