|WikiProject Computing / Hardware||(Rated Start-class)|
The end of the paragraph with this text:
"The K6-III, however, used both methods: it had 64 KiB primary cache, a massive 256 KiB on-chip, full-speed secondary cache (similar to the Celeron's but twice the size), and the variable size motherboard mounted cache on the Socket 7 main board became a tertiary level."
is confusing. It implies four levels of cache, which I don't think is accurate. Specifically I thought "on-chip" and "primary" caches were the same thing. Can anyone who knows please clarify the article? Thanks!
22.214.171.124 23:22, 27 January 2006 (UTC)
Primary cache = L1 Cache, econdary = L2-Casche, tertiary = L3-Cache, where's the fourth one ? --Denniss 01:02, 28 January 2006 (UTC)
I see. I had misread the original statement. I thought "a massive 256 KiB on-chip, full-speed secondary cache (similar to the Celeron's but twice the size)" was talking about two different caches, but I see the comma is just there to separate the adjectives. I'm not sure it would be better without the comma. Thanks for the clarification. --126.96.36.199 15:58, 30 January 2006 (UTC)
K6+ chips were lucky to hit 600 MHz, especially the III+. I personally have had 2 of them, neither of which could do 600 MHz regardless of how cool I kept them or how much voltage they received. Seems to be similar to what others have seen, from the overclocking databases around the web. K6 core has a very short 6 stage pipeline (a lot shorter than even P3) which prevents high clocks (see the 31 stage P4 Prescott!). --Swaaye 02:31, 8 April 2006 (UTC)
- A lot of people at K6Plus.com reached 600 MHz with these chips and still run them today. A lot of it was simply the luck of the draw; some of them needed 2.1 or 2.2v to get there. Some of them could hit 600 on as little as 1.8v. And some won't do it at all--my K6-III+ 450 can do 550 on 1.9, but won't make 600 even on 2.3. The record overclock, AFAIK, is 744 MHz (124*6) for a K6-III+ 550 (yes, they exist) on an FIC VA-503+. Incidentally, these chips with their L3 caches are still very capable for anything not FPU-intensive. Jsc1973 (talk) 03:32, 12 February 2009 (UTC)
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BetacommandBot 22:03, 25 October 2007 (UTC)