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Have started this as it had a link from RISC. Not very good yet, will look at more sometime. Mat-C 15:06, 17 Jul 2004 (UTC)

## This is not correct

On some RISC machines, the effective address is obtained by using the top 4 bits of the current program counter with the 28 bits given in the instruction. This can be done because RISC

(This partial comment was left by Ruud_Koot on 23:52, 22 July 2005 (UTC) according to the talk page history. I am unsure what he was getting at. --Kelerain (talk) 03:12, 14 January 2008 (UTC))
OK, it's old, but Rudd was probably getting at MIPS (See any Patterson & Hennessy) refers to pseudo direct addressing, which uses high order 4 bits of PC + a 26 bit immediate offset shifted 2 bits to form a 32 bit address. Darned if I see it mentioned on this page, while thousands of students are taught it routinely.) Did I miss it? — Preceding unsigned comment added by 209.65.48.3 (talk) 16:13, 19 November 2013 (UTC)

The part on Multi-level memory indirect states that you can get an infinite loop trying if one reference to itself. This is not true as you would have to specify a level of deepness at the instruction, else we won't know when to end, and thus it isn't an infinite loop. —Preceding unsigned comment added by 84.218.39.128 (talk) 16:32, August 24, 2007 (UTC)

Multi-level indirect can result in an infinite loop in the case when a 'word' is bigger than an address and when one of the bits unused for the address is is used to indicate another level of indirect addressing (e.g. PDP-6, PDP-10), i.e. the level of deepness is NOT specified in the instruction. The addressing chain continues for as long as the indirect bits are set in each address referenced. If one of the addresses refers to some word earlier in the chain (including possibly itself) then a infinite indirection loop appears. Murray Langton (talk) 14:56, 3 March 2008 (UTC)
On the PDP-10, if you did create an infinite-address-loop, the CPU would time out the instruction and generate an interrupt. Mzellers (talk) 23:20, 27 September 2011 (UTC)

## Index next instruction

My understanding is the machines mentioned in the "Index next instruction" section did something more like this when the "INDEX" instruction was executed:

• Normally the CPU stores each instruction it reads into the IR (instruction register) -- but when executing the "index" instruction, instead it stores the *sum* into the IR -- the sum of the instruction currently being read and the accumulator.
• Then it goes on to executing the instruction in the IR normally.

So I think the "Index next instruction" section is slightly misleading in it's "self-modifying code" comment. This is very similar to self-modifying code, but it's not exactly the same -- the sum is not actually written back out to program memory, and it works exactly the same whether the instruction is in RAM or ROM.

Could someone with more expertise confirm if my understanding is correct? (Perhaps my understanding is incorrect, and these machines, like MIX, really do require self-modifying code, which must be placed in RAM -- ROM won't work).

If my understanding is correct, could you fix the "Index next instruction" section to make it more accurate? --68.0.124.33 (talk) 04:02, 15 March 2008 (UTC)

The description in the self-modifying code article of the "EXECUTE" instruction makes it sound similar to this "INDEX" instruction. Are they really the same, or is there some significant difference I am missing? --68.0.124.33 (talk) 05:12, 25 November 2010 (UTC)

Your interpretation is correct. I have modified the article (feel free to tweak the article more if it's still unclear) Murray Langton (talk) 11:01, 25 November 2010 (UTC)

## Is 'Skip' in the right place?

'Skip' has been in the article as an addressing mode since March 2008. I agree that it should be in the article (it was the only conditional control intruction for Dec PDP-8 and Data General Nova), but I'm not sure if it is in quite the correct place within the article. Does anyone know of any current computers which use this addressing mode; if there are some significant current computers which use 'skip' I'll leave that section where it is (possibly with revised wording), if there are some relatively obscure current computers I propose to move that section further down under 'Other addressing modes', otherwise I propose to move it down under 'Obsolete addressing modes'. Murray Langton (talk) 15:25, 1 December 2008 (UTC)

Both the Atmel AVR instruction set and the PIC microcontroller instruction set has some instructions that use the "skip" addressing mode ( addressing_mode#skip ). All conditional instructions for PIC microcontrollers with "12-bit core" and the "14-bit core" use the skip addressing mode -- the only way to implement a loop on these chips is to use such a "skip" instruction to skip over an unconditional branch instruction. I've been told that Microchip sold more units of such microcontrollers in 2006 than the total unit sales of any other CPU manufacturer (still looking for a WP:RELIABLE reference that lists unit sales of the top CPU manufacturers in some recent year, even if it contradicts this rumor). I hope you agree with me that a CPU family that is apparently currently selling in higher volume than any other CPU family is "current" and "not obscure". --68.0.124.33 (talk) 19:15, 1 December 2008 (UTC)
Thank you for your prompt response. I agree that by sales volume it doesn't seem to be obscure; however I doubt if the micro-controllers you mention are all that well known, so I'll have to think about whether it stays where it is or moves down under 'Other addressing modes'. Murray Langton (talk) 21:56, 1 December 2008 (UTC)
On further thought I'm wondering if we need a new section 'Not an addressing mode' or similar to handle both the conditional instruction execution (ARM) and the 'skip' instruction. Any thoughts? Murray Langton (talk) 17:19, 2 December 2008 (UTC)
"well known": Is there some other other CPU that would be more well known, among people who solder or who use solderless breadboard? Just about every issue of Nuts and Volts for the past few years has a project for the PIC or the Atmel AVR (sometimes both). As far as I can tell, the PIC is more popular for ARRL projects than any other CPU.
The early PIC instruction set was designed decades ago, so it would be easy to say that it is "not current" -- but the same logic would force us to admit the x86 architecture instruction set is "not current" -- do we really want to admit that?
The ARM condition code and the conditional skip are functionally about the same -- so I agree that discussing them both in the same section is a good idea.
Perhaps also explicitly list in that section the normal, default, "execute the next sequential instruction" in order to comply with the WP:OBVIOUS guideline.
Perhaps call this section something like "sequential addressing"? --68.0.124.33 (talk) 21:39, 3 December 2008 (UTC)
Thanks for your suggestions. I'll meditate for a few days before changing anything. Murray Langton (talk) 08:39, 4 December 2008 (UTC)
I'm going to succumb to my completist tendencies, and add the one remaining way that the PC is modified. Because really, who wants to read a list of "Every possible way that the PC can be modified -- except for the most important one."? I'm making up a name for it off the top of my head -- we should probably find some references and adjust the name to what those references use. --68.0.124.33 (talk) 19:43, 8 December 2008 (UTC)
You mentioned the PDP-8; I see the PDP-8 and PDP-10 articles mention that they have "skip" instructions. I am tempted to mention the 4 CPUs we discussed in the "skip" section of this article. Is that a slipperly slope leading to every CPU ever built being listed under every addressing mode it supports? --68.0.124.33 (talk) 04:27, 18 December 2008 (UTC)
Unless an addressing mode is unique to a single computer family, I think it is probably better not to mention specific computers in relation to specific addressing modes. In the more general sections near the start of the article I think it may be reasonable to mention specific computer families as examples. Murray Langton (talk) 12:47, 18 December 2008 (UTC)

## memory addressing mode in 8086

there are seven addressing modes in 8086 index,base,offset,index+offset,index+base,base+offset,index+base+offset —Preceding unsigned comment added by 116.71.188.163 (talk) 08:12, 16 February 2010 (UTC)

## Comments on IBM mainframe (System/360, System/390 etc.) not correct

Until very recently there was only one way for application code to refer to operands or branch address and that was that all addresses are formed from a base address, an index address, and a displacement value. The Relative and Immediate Instruction Facility added instructions to address data using relative values. The size of the base and index values changed over the years from 24 to 31 and now 64 bits and the displacement has changed as well, but in all cases the instruction contained base and index register designations and the actual value of the displacement. Still, none of these things are called "addressing modes" in IBM terminology which by the way has a 50+ year history.

However...

In IBM terminology, addressing mode has to do with control register values and PSW (program status word) settings that determine how instructions and operands are fetched. There are 4 addressing modes in z/OS:

1 primary space mode (instructions and data fetched from current primary)
2 ASC AR mode (intructions fetched from current primary, data fetched depending on contents of access register)
3 secondary space mode (instructions fetched from current primary, data fetched from secondary)
4 home space mode (instructions and data fetched from home address space)

Applications receive control and run exclusively in mode (1) above, primary space mode. The application programmer has no knowledge of this and no control over it. None of the HLL languages or Java have any provision for changing modes nor do they have any mode awareness.

Systems software often runs in modes (2) or (3) above in addition to mode (1) above. Very rarely, pieces of operating system code run in mode (4) above, home space mode. This mode is mostly used for creating new address spaces and coordinating user work in them.

See SA22-7832-07 z/Architecture Principles of Operation at http://publibz.boulder.ibm.com/epubs/pdf/dz9zr007.pdf and SA22-7614-07 z/OS V1R11.0 MVS Programming Extended Addressability Guide at http://publibz.boulder.ibm.com/epubs/pdf/iea2a570.pdf for complete information. 77.126.191.239 (talk) 16:43, 28 April 2011 (UTC)

For better or worse, many of IBM's terms have not been adopted by the rest of the computer industry. Relatively few company speak of "storage" rather than "memory", or speak of "direct access storage devices".
In this particular case, I suspect that the term "addressing mode", used in the sense of this article, dates back to the PDP-11, as per, for example, the PDP-11/20 Handbook. In the PDP-11, the opcode did not specify whether the instruction operands came from a register or memory or, if it came from memory, how the memory address was formed; the operands were specified by a combination of a 3-bit addressing mode and a 3-bit register number. Some other instruction set architectures, such as the VAX and Motorola 68000 series, modeled themselves after the PDP-11 in that manner.
The GE 600 series used the term "address modifier", as per the GE-635 System Manual; however, it did not have the fully-orthogonal scheme that the PDP-11 did; one operand of an instruction would either be the accumulator, the multiplier/quotient register, or an index register, specified by the opcode, and the other operand would be in memory (so to move something from the AC to the MQ, you'd have to move it through memory).
In the PDP-6 and PDP-10 instruction sets, one operand would be a general-purpose register (called "accumulators"), and the other would be in "memory"; however, on the PDP-6 and earlier versions of the PDP-10, the general-purpose registers were stored in the low memory locations, so that accumulator-to-accumulator moves and arithmetic instructions were possible, and there was an option to put the GPRs into fast registers, in which case references to the low memory locations were redirected to the fast registers - later machines always had fast registers. The memory address was always formed in the same fashion, with the only "addressing mode" being an indirect mode specified by a single bit. The UNIVAC 1100/2200 series was similar, with accumulators and index registers mapped into low memory.
S/360, as the page notes, didn't have a PDP-11ish addressing mode concept; for the load/store/binary-and-floating-point arithmetic instructions, one operand is in a GPR, and the other could be in memory or a GPR, with the difference being indicated by the opcode. Memory addresses were formed by adding the displacement, the index register, and the base register (with R0 meaning "zero"), and there was no indirect addressing, so there were no explicit "addressing mode" fields.
The MIPS has three-register versions of arithmetic instructions, with all operands in registers, and immediate versions, with one operand being a constant in the instruction; there is no explicit "addressing mode" field specifying that. Load/store instructions always reference memory in the same fashion, except for a "load immediate" instruction that loads the upper part of a GPR from an immediate constant - large constants are synthesized from multiple instructions. Other RISC architectures are similar.
When comparing instruction sets, it's useful to have some concept to indicate how operands are specified, and to have a term for it. For better or worse, "addressing mode" has come to be used for that by a large number of people, IBM's use of the term nonwithstanding (does that use really date back 50 years? 50 years ago, S/360 was introduced, and S/360 didn't have address spaces - that was, I think, an S/390ism) - so it didn't have "primary space", "secondary space", etc., nor did it have 31-bit addresses - another S/390ism - and thus didn't have 24-bit, 31-bit, or 64-bit mode.)
So I'm afraid you will have to live with references to S/3x0 and z/Architecture addressing modes. You may want to add a note at the beginning that IBM used the term "addressing mode" differently, but there's nothing misleading about discussing S/3x0's ways of referring to operands in this article. Guy Harris (talk) 23:37, 13 April 2014 (UTC)