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- 1 Why erasure in units of sectors?
- 2 Read Disturb
- 3 Origin of "Flash"?
- 4 SPI flash update size
- 5 Retention
- 6 Wearout & Article Balance ??
- 7 Single voltage for program/erase/read
- 8 Flash state machines
- 9 Look out for possible copyright violations in this article
- 10 static life?
- 11 NAND/NOR clarificaiton
- 12 "The high density NAND type."
- 13 more needed about architecture
- 14 Comments and questions
- 15 Wouldn't wear leveling mapping blocks wear out first?
- 16 Radiation Effects
- 17 Congratulations
- 18 NOR program/erase logical vs. binary?
Why erasure in units of sectors?
Can someone explain why erasure can only take place one sector at a time, instead of one word at a time?
- I *think* that the erase circuitry is quite complex and to duplicate it for every cell would be prohibitively expensive in terms of chip area used.
- All the cells in a block ("sector" if you prefer) share the same source (source as in source, gate, and drain of a transistor). Erasure happens by creating a large electric field between the source and gate of the transistors, causing electrons to tunnel off the floating gate to the source.
- To erase an individual cell (one bit for SLC, usually two bits for MLC), that cell would have to have its own source connection. That would double the number of bitlines. Each would have to be routed (during layout, a phase of the design process), which would take additional design time, increase the area of the chip and/or require additional metal layers. All of those add cost.
- The second answer to your question is that because it involves tuneling, erasure is a slow process, taking seconds to complete. It's simply not acceptable to pay such a huge time cost to change the state of a single bit. When that huge time cost is amortized over the large number of bits in a block, it becomes a more acceptable trade-off. (By way of analogy, a two-core CPU performs a single task no faster than a single-core CPU, but since it can perform two tasks in parallel, it's effectively twice as fast at performing two tasks. The erase operation is effectively faster because it happens in parallel to so many bits.) Fhaigia (talk) 05:51, 16 August 2008 (UTC)
Originally, all EEPROMs *did* erase memory one word at a time. Word-at-a-time EEPROMs are still used in many devices (I think they are still used for saving BIOS settings). So it isn't "prohibitively expensive", merely "slightly more expensive".
Flash memory doesn't have individual word-select lines, using only one erase line for an entire block. So a certain number of bits of Flash memory uses less chip area (making it cost less), than the same number of bits of word-at-a-time EEPROM. I've heard some people speculate that someday FLASH will be cheaper than DRAM. (Or is it already?) --DavidCary 12:40, 22 July 2005 (UTC)
(This is in Atmel's [FAQ: What is the difference between Flash and Parallel EEPROM?] )
- yes word at a time EEPROMS do exist and do get used where only a small amount of storage is needed and simplicity is desired just as static ram is used for main system ram by many microcontrollers for similicity. However i'm pretty sure it would be prohibitively expensive to use them for general disk like storage which was what i originally meant to say. Plugwash 13:08, 22 July 2005 (UTC)
The article says 'These removable flash memory devices use the FAT file system to allow universal compatibility with computers, cameras, PDAs and other portable devices with memory card slots or ports.' This is a slight non-sequitur. They certainly _can_ be formatted with the FAT file system, but I believe you can format them as you like and do random read and writes of blocks. What is not adequately explained in the current entry is how the erase and levelling operate when formatted as FAT. FAT is a system that was invented before flash and has no knowledge of the need to erase a block before rewriting it with zero-to-one bit change. Can it be that certain writes are much much slower than others, according to whether there are zero-to-one bit changes or not ? —Preceding unsigned comment added by 184.108.40.206 (talk) 10:32, 31 August 2009 (UTC)
- File systems on FLASH devices is beyond the scope of this article. Going into a description of how the wear levelling is done specifically for a FAT FS would not be appropriate here, but instead, a link to another article or webpage that explains it would be of benefit. HumphreyW (talk) 10:39, 31 August 2009 (UTC)
- Wear levelling should be independent of the actual use. I doubt that wear levelling mechanisms implemented in actual products are based on any knowledge about FAT. Yet, in my opinion it is not stated clear enough that FAT is considered an example of "abusive and/or poorly designed hardware/software" in the context of Flash memory (the "for example..." sentence at the end of the "Block erasure" section should be more explanatory, and maybe the whole paragraph should be restructured because actually the next section is the one on "Memory wear"); actually it was never a well designed file system (the wear problem of FAT also occurs on floppy disks and was more or less regularly observed at the time floppies were widely used). --220.127.116.11 (talk) 12:56, 3 May 2010 (UTC)
This article could do with some words about Read Disturb on NAND flash memories. It's a relatively recent field of research but there is citeable work by, amongst others, NASA, Aleph1(YAFFS), Micron and a couple of patents that claim to reduce the problem. —Preceding unsigned comment added by 18.104.22.168 (talk) 13:45, 13 January 2009 (UTC)
- I just came to this page to make the same comment. I wanted to link the article write amplification to this page where I hoped to find Read Disturb covered. If I get a chance I will add what I can find. If someone else does feel free to let me know on my talk page so I can link from write amplification. § Music Sorter § (talk) 04:32, 19 June 2010 (UTC)
Origin of "Flash"?
Apologies if I missed it, but it seems that the article needs to explain the origin of "flash" in this context. It seems to me that it stems from slang usage in such a term as "in a flash", meaning in effect instantaneously. Being an old hand in electronics (I'm 74), I can well remember the quartz-windowed UV EPROMs that took tens of minutes to erase. Extremely-fast erasing could have given rise to the term "flash". Regards, Nikevich (talk) 14:54, 9 September 2010 (UTC)
- From the article: "According to Toshiba, the name "flash" was suggested by Dr. Masuoka's colleague, Mr. Shoji Ariizumi, because the erasure process of the memory contents reminded him of the flash of a camera." HumphreyW (talk) 15:20, 9 September 2010 (UTC)
SPI flash update size
The smallest sectors typically found in an "SPI flash" is 4 kB, but they can be as large as 64 kB. Since the "SPI Flash" lacks an internal SRAM buffer, the complete page must be read out and modified before written back, making it slow to manage.
This seems inaccurate to me. Recently saw a Numonyx chip (M25P128) which has 256KB sectors (64 sectors x 1024 pages x 256 bytes).
Also, if any bits are to be changed from 0 to 1, the complete sector has to be erased, while writes to previously erased space can be as small as 1 byte. 22.214.171.124 (talk) 07:46, 10 September 2010 (UTC)
I couldn't see the data retention lifetime given in the article. In good conditions, how long will flash accurately retain the data if put into storage? (eg: LTO tape rates at something like 30 years, what's the equivalent?) ‒ Jaymax✍ 11:01, 7 October 2010 (UTC)
To re-phrase, flash is non-volatile. How non-volatile? ‒ Jaymax✍ 01:06, 16 October 2010 (UTC)
It seems many manufacturers quote 10 years as a standard time. Freescale Semiconductors published an interesting study on data retention in non-volatile memory (such as flash): see http://www.freescale.com/files/microcontrollers/doc/eng_bulletin/EB618.pdf - Derekjc (talk) 09:00, 5 April 2011 (UTC)
Wearout & Article Balance ??
The first part of the article which describes the physics is good BUT IT LACKS INFORMATION ABOUT WHAT HAPPENS WHEN THE FLASH MEMORY WEARS OUT. Do the insulators get perforated? Do the cells tend to wear-out stuck-at 0, or stuck-at 1 ?? Are there any measures (cooling, lowering the programming voltage or speed) that can be used to extend flash memory life?
About 70% of the article consists of random observations about how flash memory CHIPS work. It might be good to split this up into articles about the different kind of chips, with brief overviews, because this part of the article has low info-content and is unwieldy. SystemBuilder (talk) 20:04, 15 December 2010 (UTC)
Single voltage for program/erase/read
These days one often finds NOR flash operating at ~1.8 V for read/program/erase. This situation is not explained in this article. Isn't much higher voltage required for tunnel or hot carrier injection?126.96.36.199 (talk) 16:54, 19 February 2011 (UTC)
- Yes, a much higher voltage is used internally. How can we make the flash memory#Internal charge pumps section's explanation better? --DavidCary (talk) 21:04, 8 January 2014 (UTC)
Flash state machines
The original flash devices did not have a state machine and relied on the CPU to push cycles to the chip with uS timings. If the write/erase routines got interrupted, etc. this could corrupt of damage the flash memory (circa 1993). Eventually, the NOR flash manufacturers put a state machine on flash and created the JEDEC standard. I think some information on this would add to the history section. — Preceding unsigned comment added by 188.8.131.52 (talk) 02:30, 1 September 2011 (UTC)
Look out for possible copyright violations in this article
This article has been found to be edited by students of the Wikipedia:India Education Program project as part of their (still ongoing) course-work. Unfortunately, many of the edits in this program so far have been identified as plain copy-jobs from books and online resources and therefore had to be reverted. See the India Education Program talk page for details. In order to maintain the WP standards and policies, let's all have a careful eye on this and other related articles to ensure that no material violating copyrights remains in here. --Matthiaspaul (talk) 12:58, 31 October 2011 (UTC)
the article needs a bit of work to ensure that everythng that is particular to only one technology is so identified. For example does the entire Block Erasure section apply to "specifically NOR flash"? I think not but the way it is written is ambiguous. 184.108.40.206 (talk) 21:04, 1 November 2011 (UTC)
"The high density NAND type."
This phrase appears in the first paragraph as if the reader would know what a high density NAND type is. I don't. That's too obscure a phrase to appear in the first paragraph. The first paragraph should be at a more elementary level. — Preceding unsigned comment added by Skysong263 (talk • contribs) 20:59, 2 November 2011 (UTC)
more needed about architecture
If you would read this article alone, you would think that all there is in a flash memory is the actual memory cells. This is not so. There is also control circuitry. The control circuitry is not adequately discussed here. — Preceding unsigned comment added by Skysong263 (talk • contribs) 21:11, 8 November 2011 (UTC)
Comments and questions
1. In the right column, memory should follow the sequence Historical, Early stage, In development which I believe more chronologically appropriate.
2. There should be consistency in the way Flash memory is presented in the article. At first the article talks about NAND and NOR, then it talks about NOR and NAND. I believe one sequence should be used throughout the article, possibly NOR, then NAND for chronological reasons.
3. "Dr. Masuoka presented the invention at the IEEE 1984 International Electron Devices Meeting (IEDM) held in San Francisco, California."
Since NAND Flash memory was presented in 1987, I assume that Masuoka presented NOR Flash memory in 1984. However, this is not stated in the article and the information should probably be added.
4. The last paragraph in the history section is all in the present tense. I believe it should be in the past tense since NAND was presented in 1987.
5. I think it would be nice to have a section dedicated to the comparison of NOR and NAND. The two types could be compared in two columns to give a quick idea of the two variants.
6. Flash is a proper name and it should be capitalized.
7. "For example, nearly all consumer devices ship formatted with MS-FAT file system, which pre-dates flash memory, having been designed for DOS, and disk media."
I don't see the relevance of MS-FAT within the paragraph.
8. When was wear leveling introduced for regular production?
Wouldn't wear leveling mapping blocks wear out first?
I am not yet able to find an answer to this question regarding wear leveling:
For the NAND flash memory (flash drive) to be transparent to the OS, it needs to have a controller on the chip and store a wear level mapping (LBA to PBA) on the device. The question is, where is such mapping table stored?
If the mapping table is also stored on the flash memory, it needs to be updated every time a write command is received. Therefore, the blocks that store the mapping table will wear out first, while other data blocks are not worn out yet. — Preceding unsigned comment added by 220.127.116.11 (talk) 22:28, 30 December 2011 (UTC)
- The storage format can vary from manufacturer to manufacturer (and typically isn't public knowledge), and I've never worked on such a device or filesystem. With that qualification: The translation map doesn't have to be in a fixed place, the controller just needs some way of finding it (starting by consulting a fixed place or places). One can reduce the number of erase operations needed by using the fact that changing '1' bits to '0' doesn't require an erase operation, so that there doesn't have to be an erase operation (within the metadata) every time the map changes. For example, one can use journalling techniques, where updates are implemented as appending a change record (since appending doesn't require an erase per append), and only occasionally consolidating this list of changes into a more convenient form (to reduce the number of change records to be read). Pjrm (talk) 23:43, 6 October 2012 (UTC)
- That's how JFFS2 works, for example, which is a log-structured filesystem designed to run directly on top of flash memory devices. JFFS2 just keeps appending all of the filesystem changes, with periodic garbage collection to reclaim unused space, so there's no fixed place where the filesystem's metadata is stored – it's scattered around together with the stored data. As part of the garbage collection, JFFS2 tries to "redirect" future writes to less frequently used blocks; anyway, JFFS2 doesn't employ some highly complex wear-leveling algorithms which are required to scale the whole thing to gigabytes of flash, but a similar approach is most probably used by the current commercial SSDs. In other words, commercial SSDs almost for sure wear-level the actual wear-leveling metadata. — Dsimic (talk | contribs) 04:25, 4 March 2014 (UTC)
Quartz (SiO2, silicon dioxide) can be darkened by radiation. Also, quartz has an ability to "heal" itself. There's a trick used by dishonest mineral vendors: If you bombard an ordinary quartz crystal with x-rays, the stone turns dark and can be sold as a fake "smoky quartz" at a higher price. The customer doesn't realize he's been scammed until a few months later, when the crystal starts to fade back to its original color. Obviously the x-rays are damaging the crystal bonds. In a semiconductor device, damaged bonds result in quantum traps which may allow charges (data) to escape, long after the x-ray source is turned off. And if the analogy from smoky quartz holds true, much (or all?) of that lattice damage is temporary. This should give us a few questions:
- Is x-ray damage an issue for flash drives?
- Is x-ray damage cumulative? Or does it completely heal? In other words, does it permanently reduce the storage life?
- Neglecting lattice damage, x-rays have the same erasing effect as UV light (see EPROM#Details). How large is that effect? How many x-rays (medical, dental, or airport) will erase a flash memory?
- Should travelers (esp. frequent flyers) avoid letting airport security x-ray their flash drives?
- Is data lifetime shorter at high elevations, where there's less atmosphere to shield out solar radiation?
- Non-radiation damage: If I take a flash drive and give it a million write cycles -- and then wait a year -- does the accumulated damage heal itself?
- Do silicon nitride and other gate insulators fare differently?
- Interesting questions, LessThanTwo. I started a new section flash memory#X-ray effects. Perhaps someday that section will grow big enough to answer all your questions. Currently it only partially addresses the "x-rays ... erase a flash memory" question. --DavidCary (talk) 06:00, 24 December 2013 (UTC)
This article is the most factually incorrect one I have ever seen on Wikipedia. Literally one or two errors or misrepresentations per paragraph. Bravo. — Preceding unsigned comment added by 18.104.22.168 (talk) 18:10, 20 June 2012 (UTC)
- And yet your world-renowned expertise in this issue is such that you are unable to provide a single example of what you think is wrong. Without that this is nothing more than trolling. Crispmuncher (talk) 20:19, 20 June 2012 (UTC).
- I have fair amount of experience of flash memory technologies and I do not find this article or its talks/discussions that misleading as 22.214.171.124 thinks. It describes very well the basics and also some details about the fundamentals of flash memory. — Preceding unsigned comment added by 126.96.36.199 (talk) 08:26, 30 July 2012 (UTC)
NOR program/erase logical vs. binary?
The diagram states that NOR erases to logical 0, but the text states Erase is binary '1' PRogramming NOR sets to logical 1 (in diagram) but text states Programming sets binary '0'
In every NOR chip I am familiar with, erasing a block of flash sets each and every bit in that block to a logical '1', which is binary '1', which when read looks like a "high" on the data pins. "Writing" or "programming" a byte clears selected bits to a logical '0', which is a binary '0', which when read looks like a "low" on the data pins.